Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 124

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
15.2 Read and Write Commands
15.3 4-bit and 8-bit Operation
15.4 DMA Operation
15.5 LCD Interface Registers (Base → FFFED000h)
15.5.1 Offset 000h: LCD_CFG – LCD Configuration Register
DS0200-003
LCD_RD and LCD_WR generate single reads and writes to the LCD device. The command bits self-clear
once the command is executed. Software must poll these bits and find them cleared before writing another
command. Writes to LCD_RD and LCD_WR registers while the command bits are set must be avoided.
If configured for 8-bit operation, a read or write command results in a single 8-bit operation. If configured for
4-bit operation, two 4-bit operations (High nibble first) are executed one after the other for each read or write
command. In this mode, only LCD_D[7:4] bits are used and LCD_D[3:0] bits are not used.
By setting LCD_CFG.DMA to ‘1’, a DMA request is generated if there is no pending write command. DMA
must be configured to move a single 16-bit data into LCD_WR.
31:24
23:16
15:12
11:08
07:03
Bits
02
01
00
Type
RW
RW
RW
RW
RW
RW
RW
RO
Offset
000h
004h
008h
Reset
FFh
FFh
Fh
Fh
0
0
0
0
Description
Enable Active Time (EN_ACTIVE_TIME): Specifies the number of hclks LCD_E is
driven active.
Enable Inactive Time (EN_INACTIVE_TIME):
LCD_E is driven inactive before it is enabled to be driven active again.
Address/Data Setup Time (AD_SETUP_TIME):
before rise of LCD_E
Address/Data Hold Time (AD_HOLD_TIME): Address and data hold time after fall
of LCD_E.
Reserved
DMA Enable (DMA): When set, enables DMA requests for LCD writes.
Data Bus Width (DATA_WIDTH): When set, 8-bits. When cleared, 4-bits.
LCD_ Polarity (EN_POL): When set, polarity of the LCD_E signal is ‘1’.
 00h: 2 clocks, 01h: 4 clocks, … FFh: 512 clocks
 00h: 32 clocks, 01h: 64 clocks, … FFh: 8192 clocks
 0h: 1 clock, 1h: 2 clocks, …, Fh: 16 clocks
 0h: 1 clock, 1h: 2 clocks, … Fh: 16 clocks
Register
LCD_CFG
LCD_WR
LCD_RD
Description
LCD Configuration Register
LCD Read Register
LCD Write Register
Specifies the number of hclks
Address and data setup time
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