Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 26

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
3.5.3
DS0200-003
Offset 008h: PMUCKEN – PMU Clock Enable Register
23:21
15:14
11:03
02:00
Bits
31
30
29
28
27
26
25
24
20
19
18
17
16
13
12
Type
RW`
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
Reset
111
111
FFh
11
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Description
CPU Clock Enable (CPU): Enables both CPU clocks (fclk and hclk). Forced to ‘1’ by
wake up.
USB Clock Enable (USB): Enables USB clock. Forced to ‘1’ by wake up.
Memory Controller Enable (MEMC): Enable hclk to the External Memory Controller
and SDRAM controller. Forced to ‘1’ by wake up.
SRAM/ROM Enable (SRAM_ROM): Enable hclk to the Internal SRAM and ROM.
Forced to ‘1’ by wake up.
Bridge Enable (BRDG): Enable hclk to the AHB bridge. Forced to ‘1’ by wake up.
Interrupt Controller Clock Enable (INTC): Enable hclk to the Interrupt Controller.
Forced to ‘1’ by wake up.
Random Number Generator Clock Enable (RNG): Enable hclk to the Random
Number Generator.
Reserved
GPIO “N” Enable (GPIOn): Enable hclk to GPIO “N”. Forced to ‘1’ by wake up. Bit
23 = GPIO2, bit 21 = GPIO0.
DMA Controller Clock Enable (DMA): Enable hclk to the DMA Controller
MCR Enable (MCR): Enable hclk to MCR (all 3 channels)
ADC Enable (ADC): Enable hclk to the ADC
Reserved
SmartCard Enable (SMC): Enable hclk to the SmartCard Interface
SPI “N” Enable (SPIn): Enable hclk to SPI “n”. Bit 15 = SPI1, Bit 14 = SPI0.
LCD Enable (LCD): Enable hclk to LCD Display Controller
Watchdog Enable (WDOG): Enable hclk to the Watchdog Timer
Timer “N” Enable (TMRn): Enable hclk to Timer “n”. Bit 11 = Timer 8, Bit 3 =
Timer 0.
UART “N” Enable (UARTn): Enable hclk for UART”n”. Bit 2 = UART2, Bit0 = UART0.
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