Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 148

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
17.5.2.1
17.5.2.2
17.5.2.3
DS0200-003
These registers share the same address space as UARTx_RBR and UARTx_BRG_L.
This register shares the same address space as UARTx_THR and UARTx_BRG_L.
This register shares the same addresses as UARTx_BRG_H.
31:08
07:00
31:08
07:00
31:05
Offset 000h: UARTx_THR – UART Transmit Holding Registers
Offset 000h: UARTx_RBR – UART Receive Buffer Registers
Offset 004h: UARTx_IER – UART Interrupt Enable Registers
Bits
Bits
Bits
04
03
02
01
00
Type
Type
Type
WO
WO
RW
RW
RW
RW
RW
RO
RO
RO
Reset
Reset
Reset
00h
00h
0
0
0
0
0
0
0
0
Description
Reserved
Transmit data byte (TXD): If less than eight bits are programmed for transmission,
the lower bits of the byte written to this register are selected for transmission. The
transmit FIFO is mapped at this address. You can write up to 16 bytes for transmission
at one time to this address if the FIFO is enabled by the application. If the FIFO is
disabled, this buffer is only one byte deep
Description
Reserved
Receive data byte (RXD):
Description
Reserved
Transmit Complete (TCIE): When set, transmission complete interrupt is generated
when both the transmit hold register and the transmit shift register are empty.
Modem Edge Detect (MIIE): When set, an interrupt on edge detect of status inputs
is enabled.
Line Status (LSIE): When set, line status interrupt is enabled for receive data errors:
incorrect parity bit received, framing error, overrun error, or break detection.
Transmit (TIE): When set, an interrupt is generated when the transmit FIFO/buffer is
empty indicating no more bytes available for transmission.
Receive (RIE): When set, an interrupt is generated if the FIFO/buffer contains data
ready to be read or if the receiver times out.
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