Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 56

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
7.4.1.2
7.4.1.3
DS0200-003
31:27
23:21
19:16
15:11
07:05
03:00
31:16
15:00
Offset 004h: SDR_CMD – SDRAM Command Register
Offset 008h: SDR_RFSH – SDRAM Refresh Register
Bits
Bits
26
25
24
20
10
09
08
04
Type
Type
WO
WO
RW
RW
WO
WO
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
Reset
Reset
0000h
0h
0h
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
Primary Status (PSTAT): When set, SDRAM controller enabled
Primary Controller Enable (PEN): When written to ‘1’, enables the primary SDRAM
controller
Primary Controller Disable (PDIS):
SDRAM Controller.
Reserved
Primary Command Execute (PCMDX): When written to ‘1’, invokes the command
specified in PCMD. Writes of ‘0’ have no effect. When read as ‘1’, command execution
is pending. When read as ‘0’ command is completed.
Primary Command (PCMD): Specifies the command to be executed PCMDX is set.
Reserved
Secondary Status (SSTAT): See PSTAT.
Secondary Controller Enable (SEN): See PEN.
Secondary Controller Disable (SDIS): See PDIS.
Reserved
Secondary Command Execute (SCMDX): See PCMDX.
Secondary Command (SCMD): See PCMD.
Description
Reserved
Refresh Timer (TRFC): Sets the period for AUTO_REFRESH commands generated
automatically by the SDRAM Controller in SDCLKs. Set to 0 to disable automatic refresh.
 0000: Normal Operation
 0001: NOP
 0010: PRECHARGE_ALL
 0011: LOAD_MODE_REGISTER
 0100: SELF_REFRESH
 0101: POWER_DOWN
 0110: AUTO_REFRESH
 0111: SDRAM_Zeroization
 1000 - 1111: Reserved
When written to ‘1’, disables the primary
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