Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 37

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
DS0200-003
Offset 004h: INTC_ESET – Interrupt Controller Enable Set Register
Offset 008h: INTC_ECLR – Interrupt Controller Enable Clear Register
Offset 00Ch: INTC_DFLT – Default Vector Register
Offset 010h: INTC_ISTA – Interrupt Status Register
Offset 014h: INTC_RSTA – Raw Interrupt Status Register
31:00
31:00
31:00
31:00
Bits
Bits
Bits
Bits
31:0
Bits
Type
Type
Type
Type
Type
WO
WO
RW
RO
RO
Reset
Reset
Reset
Reset
Reset
0
0
0
0
0
Description
Set (SET): Wires of ‘1’ set the corresponding bit in INTC_EN.
Description
Clear (CLR): Writes of ‘1’ clear the corresponding bit in INTC_EN.
Description
Default Vector (VEC):
INTC_FVEC in the case that no IRQ or FIQ is active when that register is read. Should
be loaded with a valid ISR address (to handle this error condition).
Description
Status (STS):
corresponds to channel 0, Bit 1 enables channel 1, etc. When cleared, the interrupt is
either not enabled or not active. When set, the interrupt is enabled and active.
Description
Status (STS): Indicates which interrupts are active before masking. Bit 0 corresponds
to channel 0, Bit 1 enables channel 1, etc. When cleared, the interrupt is active. When
set, the interrupt is not active.
Indicates which enabled (non-masked) interrupts are active. Bit 0
Contains the value to appear in either INTC_IVEC or
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