Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 127

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
16.1.3 Registers (Base → FFFEC000h)
16.1.3.1
16.1.3.2
DS0200-003
31:11
07:04
03:00
31:08
07:00
Offset 000h: WDT_CTL – Watchdog Timer Control
Offset 004h: WDT_RR – Watchdog Timer Reset
Bits
Bits
10
09
08
Type
Type
Bits
RW
RW
RW
RW
RW
Eh
Dh
Ch
RW
Offset
Fh
RO
RO
000h
004h
Table 16-2: Time Period Values for INT_PERIOD and RST_PERIOD
Reset
Reset
00h
0h
0h
Clocks
0
0
0
0
0
2
2
2
2
16
17
18
19
Description
Reserved
WDT Reset to PMU (RST_EN): When set, the watchdog timer reset to the PMU is
enabled.
WDT Interrupt (INT_EN): When set, the watchdog timer interrupt is enabled.
WDT Enable (WDT_EN): When set, the watchdog timer is enabled.
Reset Period (RST_PERIOD): If the CPU does not service the interrupt within this
time period, the WDT sends a system reset request to the PMU. See Table 16-2
Interrupt Period (INT_PERIOD):
Table 16-2
Description
Reserved
Reset (RESET): If an A5h-5Ah sequence is written to WDT_RR before the reset
period lapses, the interrupt timer is reset to its initial count value and counting
resumes.
WDT_CTL
Register
WDT_RR
 A5h: The first write value required to reset the WDT Timer prior to a system
 5Ah: The second write value required to reset the WDT Timer prior to a system
reset time-out.
reset time-out.
Bits
Bh
Ah
9h
8h
Description
Watchdog Timer Control Register
Watchdog Timer Reset Register
Clocks
2
2
2
2
20
21
22
23
Bits
7h
6h
5h
4h
Time period before sending an interrupt. See
Clocks
2
2
2
2
24
25
26
27
Bits
3h
2h
1h
0h
Clocks
2
2
2
2
28
29
30
31
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