Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 28
Z32AN00NW200SG
Manufacturer Part Number
Z32AN00NW200SG
Description
IC ARM922T MCU 200MHZ 256-BGA
Manufacturer
Zilog
Series
Encore!® 32r
Datasheet
1.Z32AN00NW200SG.pdf
(196 pages)
Specifications of Z32AN00NW200SG
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
Peripherals
DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
For Use With
269-4713 - KIT DEV ENCORE 32 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
269-4717
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Z32AN Series Data Sheet
3.5.6
DS0200-003
Offset 01Ch: PMUCFG – PMU Configuration Register
29:27
21:19
15:03
Bits
31
30
26
25
24
23
22
18
17
16
02
01
00
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
Reset
000
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
ADC Power Disable (ADC_DIS): When set, enables power to the ADC.
MCR “N” Power Enable (MCRn_IEN): Bit 30 = MCR2, bit 28= MCR0. When set,
enables power to the MCR “N” analog front end. Note: all MCR power enable bits must
be set to use the MCR
MCR ADC Power Enable (MCR_ADC_EN): When set, enables power to the MCR
ADC. Note: All MCR Power Enable bits must be set to use the MCR
MCR VREF Power Enable (MCR_VREF_EN): When set, enables power to the MCR
voltage reference. Note: All MCR Power Enable bits must be set to use the MCR
MCR IREF Power Enable (MCR_IREF_EN): When set, enables power to the MCR
current reference. Note: All MCR Power Enable bits must be set to use the MCR
USB Power Enable (USB_EN): When set, enables power to USB
USB Suspend (USB_SUSP): When set, place USB in suspend mode
Reserved
USB Wake Enable (USB_WAKE): When set, enable wake when USB not IDLE.
GPIO Wake Enable (GPIO_WAKE): When set, enables wake on GPIO wake.
RTC Wake Enable (RTC_WAKE): When set, enables wake on RTC wake.
Reserved
ROM MMU Table Write mode (ROM_MMU_BUFF): When set, disables the buffer-
able bit in the ROM MMU table. If the buffer-able bit is set, writes that hit in the cache
are marked dirty and written back later. If the buffer-able bit is clear, writes that hit in
the cache are written through and memory is updated immediately. The setting of this
bit is the inverse of the buffer-able bit that appears in the cacheable region of the ROM
MMU table. (See section 5.6.4)
Reserved
SRAM Re-Map (SRAM_REMAP):
memory. When set, SRAM appears at the bottom of memory
When cleared, ROM appears at the bottom of
Page 15
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