Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 177

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
19.8.5 Offset 010h: USB_OTG_ISTAT – OTG Interrupt Status Register
19.8.6 Offset 014h: USB_OTG_IEN – OTG Interrupt Control Register
DS0200-003
This register enables the corresponding interrupt status bits defined in USB_OTG_ISTAT.
31:08
Bits
31:08
07
06
05
04
03
02
01
00
Bits
07
06
05
04
03
02
01
00
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
Type
Type
RO
RO
RO
RW
RW
RW
RW
RW
RW
RO
RO
RO
Reset
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
ID: This bit is set when a change in the ID Signal from the USB connector is sensed.
MS1: This bit is set when the 1 millisecond timer expires.
LINE_STATE: Set when USB_CTRL.SE0 and USB_CTRL.J are stable for 1ms, and the
value is different from the last time that line state was stable.
between SE0 and J, SE0 and K and J and K.
connect and data line pulse signaling.
Reserved
BSESSV: Set when a change in V
BSESSE: Set when a change in VBUS is detected on a “B” device.
Reserved
AVBUSV: This bit is set when a change in VBUS is detected on an “A” device.
Description
Reserved
ID: Enables USB_OTG_ISTAT.ID to generate an interrupt
MS1: Enables USB_OTG_ISTAT.MS1 to generate an interrupt.
LINE_STATE: Enables USB_OTG_ISTAT.LINE_STATE to generate an interrupt.
Reserved
BSESSV: Enables USB_OTG_ISTAT.BSESSV to generate an interrupt.
BSESSE: Enables USB_OTG_ISTAT.BSESSE to generate an interrupt.
Reserved
AVBUSV: Enables USB_OTG_ISTAT.AVBUSV to generate an interrupt.
BUS
is detected.
Useful for detecting reset, resume,
Set on transitions
Page 164