Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 49

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
7.2.6
7.2.7
7.2.8
7.2.8.1
7.2.8.2
DS0200-003
3 power savings modes are available to the SDRAM controller:
While the SDRAM controller is operating on the external memory (nCS = 0 and CKE = 1), SDRAM is not in a
power saving mode. No matter what power down state is active, any access causes an immediate transition
to this state. For the Active Standby and Auto Refresh states, there is no performance penalty associated
with the access. For the Power-Down and Self-Refresh states, there is a delay to transition to the Active
state.
Multiplexing the bank, row and column bits is described in section 7.2.2. Within the EBI, additional pin
multiplexing and de-multiplexing occurs. For more details, see section 7.1.
Initialization is achieved through a sequence of delays and SDRAM commands. This sequence is device
dependent, but a general sequence is provided below; this is an example initialization only – refer to the
SDRAM datasheet for a more specific initialization sequence.
AUTO_REFRESH cycles are performed automatically at a period based upon SDR_RFSH. The setting of
the timer register depends on SDCLK frequency as well as the number of rows and t
The register must be set according to the following equation:
Additionally, the user can perform a refresh by sending the AUTO_REFRESH command of SDR_CMD.
Power Saving Modes
Pin Multiplexing
Programmer’s Guide
Initialization
Refresh Control



►Note: DQMU, DQML, nRAS, nCAS, and nWE are also multiplexed on Address pins 19-18 and
15-13 for the secondary interface.
1.
2.
3.
4.
5.
6.
Pre-charge Standby: This state is the same as Active Standby, except that all banks are
closed. In this case, nCS = 1 and CKE = 1. To close all banks, This is entered via a
PRECHARGE_ALL command to SDR_CMD, or when the refresh timer times out. Apart from
periodic refreshes generated by the SDRAM Controller, no commands are issued to the
SDRAM. There is no penalty delay incurred when a memory access invokes Active Operation.
Pre-charge Power Down: In this mode, all banks are closed and nCS = 1 and CKE = 0. This
state is entered either by a POWER_DOWN command issued to SDR_CMD or by the power-
down timer of SDR_APD. In this mode, SDCLK may be configured to be properly disabled and
re-enabled automatically.
Self Refresh: In this mode, all banks are closed and nCS = 1 and CKE = 0. This state is
entered either by a SELF_REFRESH command issued to SDR_CMD or by the power-down
timer of SDR_APD. In this mode, SDCLK may be configured to be properly disabled and re-
enabled automatically.
Set the SDRAM clock enable and frequency via PMU registers (Power and SDRAM clocks).
Configure the SDRAM Controller by writing to SDR_CFG and SDR_RFSH.
Wait for 100 µs (time required for the SDRAM Controller to initialize). During this time, the
SDRAM controller will drive CS inactive (COMMAND_INHIBIT).
Initiate a PRECHARGE_ALL command to the SDRAM by writing to SDR_CMD.
Initiate two AUTO_REFRESH commands to the SDRAM by writing twice to SDR_CMD.
Initiate a LOAD_MODE_REGISTER command to the SDRAM by writing to SDR_CMD. By
design, the SDRAM Controller waits at least two clocks before issuing a subsequent
command.
REF
for the SDRAM.
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