Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 47

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
7.2
7.2.1
7.2.2
DS0200-003
0
1
SDRAM Controller
Key features of SDRAM Controller:
Once configured, the SDRAM controller interfaces to a x16 SDRAM configuration and allows any AHB
master to access memory transparently. Byte, half-word and word accesses are supported. In addition,
burst accesses are supported. AUTO_REFRESH commands are issued automatically based on the user
configuration. Power saving modes can be controlled by user commands and configuration.
SDR_CFG
Operation
Address Mapping




00
01
10
00
01
10
Support for 64 Mb, 128 Mb, 256 Mb and 512 Mb SDRAM devices
Direct interface for two 16-bit SDRAM devices (if both interfaces are used, the SDRAM used
must be the same on each interface)
Programmable timing parameters
Support for entering and exiting power-down modes
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
ROW[12:0]
B[1:0]
ROW[11:0]
ROW[10:0]
ROW[12:0]
ROW[11:0]
ROW[12:0]
ROW[10:0]
ROW[12:0]
ROW[11:0]
ROW[11:0]
ROW[10:0]
ROW[12:0]
ROW[10:0]
ROW[12:0]
ROW[11:0]
ROW[11:0]
ROW[10:0]
ROW[12:0]
ROW[10:0]
ROW[11:0]
ROW[10:0]
ROW[12:0]
ROW[11:0]
ROW[10:0]
Memory Address
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
B[1:0]
COLUMN[10:0]
COLUMN[10:0]
COLUMN[10:0]
COLUMN[10:0]
COLUMN[10:0]
COLUMN[10:0]
COLUMN[9:0]
COLUMN[9:0]
COLUMN[9:0]
COLUMN[9:0]
COLUMN[9:0]
COLUMN[9:0]
COLUMN[8:0]
COLUMN[8:0]
COLUMN[8:0]
COLUMN[8:0]
COLUMN[8:0]
COLUMN[8:0]
COLUMN[7:0]
COLUMN[7:0]
COLUMN[7:0]
COLUMN[7:0]
COLUMN[7:0]
COLUMN[7:0]
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