Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 8

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
DS0200-003
Chapter 11: Real-Time Clock (RTC) ............................................................................ 93
Chapter 12: Random Number Generator (RNG) ..................................................... 101
Chapter 13: SHA-1 ...................................................................................................... 103
Chapter 14: Analog-to-Digital Converter (ADC) ..................................................... 105
Chapter 15: LCD Interface ......................................................................................... 110
11.1 Real-Time Clock Time/Counter Registers........................................................................................ 93
11.2 RTC Alarm............................................................................................................................................. 93
11.3 RTC Wake ............................................................................................................................................. 93
11.4 RTC Oscillator Source ......................................................................................................................... 93
11.5 RTC Battery Backup............................................................................................................................ 93
11.6 RTC Reset.............................................................................................................................................. 93
11.7 Oscillator External Circuit................................................................................................................... 94
11.8 RTC Registers (Base → FFFFB000h).................................................................................................... 94
11.9 RTC Locking ......................................................................................................................................... 99
12.1 Programming Guide......................................................................................................................... 101
12.2 RNG Registers (Base → FFFFA000h)................................................................................................ 101
13.1 Programming Guide......................................................................................................................... 103
13.2 SHA-1 Registers (Base → FFFF9000h) .............................................................................................. 103
14.1 Voltage Reference........................................................................................................................... 105
14.2 Clock / Sample Rate ........................................................................................................................ 105
14.3 Modes of Operation......................................................................................................................... 105
14.4 DMA Operation................................................................................................................................. 105
14.5 Registers (Base → FFFF2000h).......................................................................................................... 106
15.1 Interface Timing ................................................................................................................................ 110
15.2 Read and Write Commands........................................................................................................... 111
15.3 4-bit and 8-bit Operation ................................................................................................................ 111
15.4 DMA Operation................................................................................................................................. 111
15.5 LCD Interface Registers (Base → FFFED000h)............................................................................... 111
11.8.1 Current Time Registers......................................................................................................94
11.8.2 Alarm Registers .................................................................................................................96
11.8.3 Control Registers...............................................................................................................98
11.9.1 Address FFFFC00Ch: RTC_APB_STA – RTC APB Status Register .....................................99
11.9.2 Address FFFFC694h: RTC_LCK1 – RTC Lock 1 Register.................................................100
11.9.3 Address FFFFC698h: RTC_LCK2 – RTC Lock 2 Register.................................................100
12.2.1 Offset 000h: RNG_DATA – Random Number Generator Data Register ....................101
12.2.2 Offset 004h: RNG_CTRL – Random Number Generator Control Register .................102
13.2.1 Offset 000h: SHA1_H – Hashed Value ...........................................................................103
13.2.2 Offset 014h: SHA1_DATA_IN – Data In ..........................................................................103
13.2.3 Offset 018h: SHA1_CONTROL – SHA-1 Control .............................................................104
13.2.4 Offset 01Ch: SHA1_STATUS – SHA-1 Status ....................................................................104
13.2.5 Offset 020h: SHA1_WH – SHA-1 Initialization Value ......................................................104
14.3.1 Continuous Rotating ......................................................................................................105
14.3.2 Single Shot .......................................................................................................................105
14.5.1 Offset 000h: ADC_CFG – ADC Configuration Register ...............................................106
14.5.2 Offset 004h: ADC_CMD – ADC Command Register...................................................107
14.5.3 Offset 008h: ADC_FIFO – ADC FIFO ..............................................................................107
14.5.4 Offset 00Ch: ADC_INT – ADC Interrupt Register ..........................................................108
14.5.5 Offset 010h: ADC_STA – ADC Status Register...............................................................109
15.1.1 Read Cycle .....................................................................................................................110
15.1.2 Write Cycle......................................................................................................................110
15.5.1 Offset 000h: LCD_CFG – LCD Configuration Register .................................................111
15.5.2 Offset 004h: LCD_RD – LCD Read Register ..................................................................112
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