UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 91

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.3.4 Register addressing
3.4 Operand Address Addressing
during instruction execution.
3.4.1 Implied addressing
[Function]
[Illustration]
The following methods are available to specify the register and memory (addressing) to undergo manipulation
[Function]
[Operand format]
[Description example]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/Kx2-L microcontroller instruction words, the following instructions employ implied addressing.
Because implied addressing can be automatically determined with an instruction, no particular operand format is
necessary.
In the case of MULU X
With an 8-bit
example, the A and AX registers are specified by implied addressing.
MULU
DIVUW
ADJBA/ADJBS
ROR4/ROL4
Instruction
8-bit multiply instruction, the product of the A register and X register is stored in AX. In this
A register for multiplicand and AX register for product storage
AX register for dividend and quotient storage
A register for storage of numeric values that become decimal correction targets
A register for storage of digit data that undergoes digit rotation
rp
PC
7
15
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 3 CPU ARCHITECTURE
A
Register to Be Specified by Implied Addressing
0
8
7
7
X
0
0
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