UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 701

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
<R>
<R>
<R>
<R>
Caution The pins mounted depend on the product. Refer to Caution 3 at the beginning of this chapter.
(2) PGA
Note Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after the
(3) Operational amplifier 0
Note Time required until a state is entered where the DC and AC specifications of the operational amplifier 0 are
Input offset voltage
Input voltage range
Maximum output voltage
Gain
Slew rate
Operation stabilization wait time
Input offset voltage
Common-mode voltage input
rejection ratio
Power supply voltage rejection ratio PSRR
Output voltage, high
Output voltage, low
Common-mode input voltage
Slew rate
Input noise spectral density (Inoise)
Phase margin
Large-amplitude voltage gain
Gain-bandwidth product
Operation stabilization wait time
(T
(T
A
A
PGA operation has been enabled (PGAEN = 1).
satisfied after the operational amplifier 0 operation has been enabled (OPAMP0E = 1).
= 40 to +85 C, 2.7 V
= 40 to +85 C, 2.2 V
Parameter
Parameter
CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Note
Note
AV
V
V
V
V
SR
SR
t
V
CMRR
V
V
V
SR
AV
GBW
t
Symbol
DD
PGA
OP0
Symbol
IOPGA
IPGA
OPGA
IOP0
OHOP0
OLOP0
ICMOP0
REF
OP0
FPGA
RPGA
OP0
OP0
5.5 V, 2.2 V
OP0
OP0
Preliminary User’s Manual U19111EJ2V1UD
V
DD
Falling edge
Rising edge
AV
I
AV
I
AV
AV
AV
AV
AV
AV
AV
AV
SOURCEOP0
SOURCEOP0
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
5.5 V, V
= 3.0 V/2.2 V,
= 3.0 V/2.2 V,
= 3.0 V/2.2 V
= 3.0 V
= 5.0 V
= 3.0 V, V
= 3.0 V, V
= 3.0 V, V
= 3.0 V
= 5.0 V/3.0 V/2.2 V
AV
= 500 A
= 500 A
SS
REF
Conditions
Conditions
4.0 V
2.7 V
4.0 V
2.7 V
= AV
IN
IN
IN
= 0.1 V
= AV
= AV
5.5 V, V
SS
AV
AV
AV
AV
REF
REF
= 0 V)
REF
REF
REF
REF
/2 V@1 kHz
0.6 V
SS
< 4.0 V
< 4.0 V
5.5 V
5.5 V
= AV
SS
= 0 V)
AV
0.1AV
0.1AV
MIN.
REF
MIN.
gain
0
3.5
2.5
2
4
0.2
REF
REF
4, 8, 16, 32
/
TYP.
100
TYP.
1.8
2.0
2.6
70
70
73
60
55
60
10
5
AV
0.9AV
0.9AV
MAX.
MAX.
REF
gain
0.1
10
10
3
REF
REF
0.6
/
times
MHz
V/ s
V/ s
V/ s
V/ s
V/ s
V/ s
nV
Unit
Unit
deg
mV
mV
dB
dB
dB
V
V
V
V
V
H
s
s
701
/
z

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