UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 518
UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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15.6 Timing Charts
slave devices as its communication partner.
(IICAS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
transmit data is transferred to the SO latch and is output (MSB first) via the SDAA0 pin.
518
When using the I
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0
Figures 15-34 and 15-35 show timing charts of the data communication.
The IICA shift register (IICA)’s shift operation is synchronized with the falling edge of the serial clock (SCLA0). The
Data input via the SDAA0 pin is captured into IICA at the rising edge of SCLA0.
2
C bus mode, the master device outputs an address via the serial bus to select one of several
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
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