UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 209
UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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5.6.7 Condition before changing CPU clock and processing after changing CPU clock
KY2-L,
KA2-L,
KB2-L,
KC2-L
KC2-L
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Remark Only 78K0/KC2-L is provided with a subsystem clock.
Before Change
Internal high-
speed
oscillation
clock
X1 clock
External main
system clock
Internal high-
speed
oscillation
clock
X1 clock
External main
system clock
Internal high-
speed
oscillation
clock
X1 clock
External main
system clock
XT1 clock,
external
subsystem
clock
CPU Clock
X1 clock
External main
system clock
Internal high-
speed
oscillation
clock
XT1 clock
External
subsystem
clock
Internal high-
speed
oscillation
clock
X1 clock
External main
system clock
After Change
Stabilization of X1 oscillation
Enabling input of external clock from
EXCLK pin
Oscillation of internal high-speed oscillator
Stabilization of XT1 oscillation
Enabling input of external clock from
EXCLKS pin
Oscillation of internal high-speed oscillator
and selection of internal high-speed
oscillation clock as main system clock
Stabilization of X1 oscillation and
selection of high-speed system clock as
main system clock
Enabling input of external clock from
EXCLK pin and selection of high-speed
system clock as main system clock
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
MSTOP = 0, OSCSEL = 1, EXCLK = 0
After elapse of oscillation stabilization
MSTOP = 0, OSCSEL = 1, EXCLK = 1
RSTOP = 0
XTSTART = 0, EXCLKS = 0,
After elapse of oscillation stabilization
XTSTART = 0, EXCLKS = 1,
OSCSELS = 1
RSTOP = 0, MCS = 0
MSTOP = 0, OSCSEL = 1, EXCLK = 0
After elapse of oscillation stabilization
MCS = 1
MSTOP = 0, OSCSEL = 1, EXCLK = 1
MCS = 1
time
OSCSELS = 1, or XTSTART = 1
time
time
Table 5-7. Changing CPU Clock
Condition Before Change
External main system clock input can be
disabled (MSTOP = 1).
External main system clock input can be
disabled (MSTOP = 1).
Internal high-speed oscillator can be
stopped (RSTOP = 1).
Internal high-speed oscillator can be
stopped (RSTOP = 1).
X1 oscillation can be stopped (MSTOP = 1).
External main system clock input can be
disabled (MSTOP = 1).
Operating current can be reduced by
stopping internal high-speed oscillator
(RSTOP = 1).
X1 oscillation can be stopped (MSTOP = 1).
Operating current can be reduced by
stopping internal high-speed oscillator
(RSTOP = 1).
X1 oscillation can be stopped (MSTOP = 1).
XT1 oscillation can be stopped or external
subsystem clock input can be disabled
(OSCSELS = 0).
XT1 oscillation can be stopped or external
subsystem clock input can be disabled
(OSCSELS = 0).
XT1 oscillation can be stopped or external
subsystem clock input can be disabled
(OSCSELS = 0).
Processing After Change
209
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