UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 447
UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Therefore, the maximum receivable baud rate at the transmission destination is as follows.
Similarly, the maximum permissible data frame length can be calculated as follows.
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
The permissible baud rate error between UART6 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
10
11
4
8
20
50
100
255
Minimum permissible data frame length: FLmin = 11
Division Ratio (k)
FLmax = 11
FLmax =
BRmax = (FLmin/11)
BRmin = (FLmax/11)
2. k: Set value of BRGC6
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
21k – 2
20k
FL
Table 14-6. Maximum/Minimum Permissible Baud Rate Error
FL
k + 2
2
Maximum Permissible Baud Rate Error
k
11
1
1
CHAPTER 14 SERIAL INTERFACE UART6
=
=
FL =
21k + 2
21k
22k
Preliminary User’s Manual U19111EJ2V1UD
20k
21k
+2.33%
+3.53%
+4.26%
+4.56%
+4.66%
+4.72%
2
2
Brate
Brate
k
2
FL
FL
k
2k
2
Minimum Permissible Baud Rate Error
FL =
21k + 2
2k
2.44%
3.61%
4.31%
4.58%
4.67%
4.73%
FL
447
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