UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 336

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.4.2 Setting overflow time of watchdog timer
starts counting again by writing “ACH” to WDTE during the window open period before the overflow time.
336
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
The following overflow time is set.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
Remarks 1. f
5. The watchdog timer continues its operation during self-programming and EEPROM
WDCS2
depending on the set value of bit 0 (LSROSC) of the option byte.
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is not cleared to 0 but starts counting from the value at
which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the
internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops
operating. At this time, the counter is not cleared to 0.
emulation of the flash memory.
delayed. Set the overflow time and window size taking this delay into consideration.
In HALT mode
In STOP mode
0
0
0
0
1
1
1
1
2. ( ): f
2. The watchdog timer continues its operation during self-programming and EEPROM
IL
is prohibited.
emulation of the flash memory. During processing, the interrupt acknowledge time
is delayed.
consideration.
: Internal low-speed oscillation clock frequency
WDCS1
Table 9-3. Setting of Overflow Time of Watchdog Timer
IL
0
0
1
1
0
0
1
1
= 33 kHz (MAX.)
Watchdog timer operation stops.
Oscillator Can Be Stopped by Software)
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 9 WATCHDOG TIMER
WDCS0
Set the overflow time and window size taking this delay into
LSROSC = 0 (Internal Low-Speed
0
1
0
1
0
1
0
1
2
2
2
2
2
2
2
2
7
8
9
10
12
14
15
17
/f
/f
/f
During processing, the interrupt acknowledge time is
/f
/f
/f
/f
/f
IL
IL
IL
IL
IL
IL
IL
IL
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(124.12 ms)
(496.48 ms)
(992.97 ms)
(3.97 s)
Overflow Time of Watchdog Timer
Watchdog timer operation continues.
LSROSC = 1 (Internal Low-Speed
Oscillator Cannot Be Stopped)
TM