UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 457

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
Note The signal of this bit is invalid while IICE0 is 0.
Cautions concerning set timing
Condition for clearing (STT0 = 0)
STT0
device
For master reception:
For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
Cannot be set to 1 at the same time as SPT0.
Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Cleared by loss in arbitration
Cleared after start condition is generated by master
Cleared by LREL0 = 1 (exit from communications)
When IICE0 = 0 (operation stop)
Reset
Cleared by setting STT0 to 1 while communication
reservation is prohibited.
0
1
Note
2. IICRSV: Bit 0 of IICA flag register 0 (IICAF0)
Do not generate a start condition.
When bus is released (in STOP mode):
When a third party is communicating:
In the wait state (when master device):
Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (3/4)
Generate a start condition (for starting as master). When the SCLA0 line is high level, the SDAA0 line
Generates a restart condition after releasing the wait.
is changed from high level to low level and then the start condition is generated. Next, after the rated
amount of time has elapsed, SCLA0 is changed to low level (wait state).
STCF:
When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
When communication reservation function is disabled (IICRSV = 1)
STCF is set to 1 and information that is set (1) to STT0 is cleared. No start condition is generated.
Bit 7 of IICA flag register 0 (IICAF0)
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when
ACKE0 has been cleared to 0 and slave has been notified of final reception.
during the wait period that follows output of the ninth clock.
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
Start condition trigger
Condition for setting (STT0 = 1)
Set by instruction
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