UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 637

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(b) When LVI default start function enabled is set (LVISTART = 1)
<1> Start in the following initial setting state.
<2> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default
<3> Release the interrupt mask flag of LVI (LVIMK).
<4> Execute the EI instruction (when vector interrupts are used).
Figure 22-9 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <3> above.
Cautions 1. Even when the LVI default start function is used, if it is set to LVI operation prohibition by
When using 8-bit memory manipulation instruction:
When using 1-bit memory manipulation instruction:
When starting operation
When stopping operation
Either of the following procedures must be executed.
Write 00H to LVIM.
Clear LVION to 0.
value).
2. When the LVI default start function (bit 0 (LVISTART) of 0081H = 1) is used, the LVIRF flag
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply
voltage (V
V
Set the low-voltage detection level selection register (LVIS) to 0FH (V
Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
Set bit 0 (LVIF) of LVIM to 0 (Detects falling edge “Supply voltage (V
(V
the software (LVION (bit 7 of LVIM register) = 0), it operates as follows:
For details of RESF, refer to CHAPTER 20 RESET FUNCTION.
may become 1 from the beginning due to the power-on waveform.
DDLVI
LVI
Does not perform low-voltage detection during LVION = 0.
If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts
after reset release. There is a period when low-voltage detection cannot be performed
normally, however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 s max.,
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting
for the LVI stabilization time.
)”)
(LVI default start detection voltage) = 1.91 V 0.1 V
DD
))
CHAPTER 22 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U19111EJ2V1UD
LVI
DD
= 1.91 V 0.1 V ).
)
LVI detection voltage
637