UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 675

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Call/return
Stack
manipulate
Unconditional
branch
Conditional
branch
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
CALL
CALLF
CALLT
BRK
RET
RETI
RETB
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
!addr16
!addr11
[addr5]
PSW
rp
PSW
rp
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16
Operands
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 27 INSTRUCTION SET
Bytes
3
2
1
1
1
1
1
1
1
1
1
4
2
2
3
2
2
2
2
2
2
Note 1
7
5
6
6
6
6
6
2
4
2
4
6
6
8
6
6
6
6
Clocks
Note 2
10
8
8
(SP
PC
(SP
PC
SP
(SP
PC
SP
(SP
(SP
PC
PC
SP
PC
PSW
PC
PSW
(SP
(SP
SP
PSW
rp
SP
SP
SP
AX
PC
PC
PCH
PC
PC
PC
PC
H
15
H
L
H
H
H
1)
1)
11
1)
1)
3)
1)
1)
SP
SP
SP + 2
SP
(SP + 1), rp
SP + 2
word
AX
SP
addr16, SP
addr16
PC + 2 + jdisp8
PC + 2 + jdisp8 if CY = 1
PC + 2 + jdisp8 if CY = 0
PC + 2 + jdisp8 if Z = 1
PC + 2 + jdisp8 if Z = 0
(003EH), SP
(addr5 + 1), PC
(SP + 1), PC
(SP + 1), PC
(SP + 1), PC
A, PC
(SP + 2), SP
(SP + 2), SP
(SP), SP
00001, PC
(PC + 3)
(PC + 2)
(PC + 1)
PSW, (SP
(PC + 1)
PSW, SP
rp
2
2
2
CPU
H
L
, (SP
) selected by the processor clock
Operation
L
X
H
H
H
L
L
L
L
SP + 1
, PC
, (SP
, (SP
, (SP
SP
10
2)
(SP),
L
SP
2)
(SP),
(SP),
(SP),
SP
SP + 3
SP + 3
0
H
2
(addr5),
rp
2)
2)
2)
3, IE
addr11,
L
(PC + 1)
(003FH),
1
,
(PC + 3)
(PC + 2)
(PC + 1)
0
H
,
L
L
L
,
,
,
R R R
R R R
R R R
Z AC CY
Flag
675