UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 366

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.3 Registers Controlling Clock Output Controller
366
The following two registers are used to control the clock output controller.
(1) Clock output selection register (CKS)
Notes 1.
Caution Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
Address: FF40H
Symbol
CKS
Clock output selection register (CKS)
Port mode register 4 (PM4)
This register sets output enable/disable for clock output (PCL) and sets the output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears CKS to 00H.
Figure 11-2. Format of Clock Output Selection Register (CKS) (48-pin products of 78K0/KC2-L)
2.
If the peripheral hardware clock (f
f
If internal high-speed oscillation clock frequency is set to 8 MHz (R4M8MSEL = 0) by option byte and
the peripheral hardware clock (f
0) when 1.8 V
prohibited.
PRS
V
V
DD
DD
CLOE
operating frequency varies depending on the supply voltage.
CCS3
7
0
0
1
0
0
0
0
0
0
0
0
1
= 2.7 to 5.5 V: f
= 1.8 to 2.7 V: f
After reset: 00H
Clock division circuit operation stopped. PCL fixed to low level.
Clock division circuit operation enabled. PCL output enabled.
CCS2
V
Other than above
DD
6
0
0
0
0
0
1
1
1
1
0
CHAPTER 11 CLOCK OUTPUT CONTROLLER
< 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: f
PRS
PRS
R/W
Preliminary User’s Manual U19111EJ2V1UD
10 MHz
5 MHz
CCS1
5
0
0
0
1
1
0
0
1
1
0
PRS
PRS
) operates on the internal high-speed oscillation clock (f
) operates on the high-speed system clock (f
PCL output enable/disable specification
CLOE
CCS0
<4>
0
1
0
1
0
1
0
1
0
f
f
f
f
f
f
f
f
f
Setting prohibited
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
SUB
CCS3
Note 2
/2
/2
/2
/2
/2
/2
/2
3
2
3
4
5
6
7
32.768 kHz
32.768 kHz
PCL output clock selection
f
SUB
CCS2
=
2
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
4 MHz
f
PRS
CCS1
=
1
XH
Note 1
) (XSEL = 1), the
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.25 kHz
78.125 kHz
10 MHz
f
CCS0
PRS
IH
0
=
) (XSEL =
PRS
) is