UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 487
UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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(2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register 0 (IICAF0) =
1)
When bit 1 (STT0) of IICA control register 0 (IICACTL0) is set to 1 when the bus is not used in a
communication during bus communication, this request is rejected and a start condition is not generated. The
following two statuses are included in the status where bus is not used.
To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of IICF). It
takes up to 5 clocks until STCF is set to 1 after setting STT0 = 1. Therefore, secure the time by software.
When arbitration results in neither master nor slave operation
When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LREL0) of IICACTL0 to 1 and saving communication)
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
487
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