UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 337

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
9.4.3 Setting window open period of watchdog timer
byte (0080H). The outline of the window is as follows.
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option
Example: If the window open period is 25%
Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the
The window open period to be set is as follows.
Counting
starts
If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting
again.
Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal
reset signal is generated.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
overflow time regardless of the timing of the writing, and the watchdog timer starts counting
again.
WINDOW1
0
0
1
1
Internal reset signal is generated
if ACH is written to WDTE.
Window close period (75%)
2. The watchdog timer continues its operation during self-programming and EEPROM
is prohibited.
emulation of the flash memory. During processing, the interrupt acknowledge time
is delayed.
consideration.
Table 9-4. Setting Window Open Period of Watchdog Timer
WINDOW0
1
0
1
0
25%
50%
75%
100%
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 9 WATCHDOG TIMER
Set the overflow time and window size taking this delay into
Window Open Period of Watchdog Timer
Counting starts again when
ACH is written to WDTE.
Window open
period (25%)
Overflow
time
337

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