UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 478

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5.12 Arbitration
to 1), communication among the master devices is performed as the number of clocks are adjusted until the data
differs. This kind of operation is called arbitration.
(IICAS0) is set (1) via the timing by which the arbitration loss occurred, and the SCLA0 and SDAA0 lines are both set
to high impedance, which releases the bus.
stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
control.
478
Transfer lines
When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in the IICA status register 0
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a
For details of interrupt request timing, refer to 15.5.8 Interrupt request (INTIICA0) generation timing and wait
Remark
Master 1
Master 2
SDAA0
SDAA0
SDAA0
SCLA0
SCLA0
SCLA0
STD0: Bit 1 of IICA status register 0 (IICAS0)
STT0: Bit 1 of IICA control register 0 (IICACTL0)
Figure 15-22. Arbitration Timing Example
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
Master 1 loses arbitration
Hi-Z
Hi-Z