UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 731

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 12 A/D CONVERTER
p. 383
p. 384
p. 387
p. 391
CHAPTER 13 OPERATIONAL AMPLIFIERS
p. 399
p. 400
p. 402
p. 403
p. 405
p. 406
CHAPTER 14 SERIAL INTERFACE UART6
p. 414
p. 421
p. 425
p. 429
CHAPTER 15 SERIAL INTERFACE IICA
p. 468
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
Throughout
pp. 534, 535
p. 550
CHAPTER 17 INTERRUPT FUNCTIONS
p. 551
p. 552
p. 556
pp. 561 to
563
pp. 566 to
568
pp. 571 to
573
CHAPTER 19 STANDBY FUNCTION
p. 591
Remark “Classification” in the above table classifies revisions as follows.
Page
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Modification of Table 12-3 Setting Functions of P10/ANI8/AMP1-, P12/ANI10/AMP1+ Pins
Modification of Table 12-5 Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+ Pins
Deletion of Caution 2 in 12.4.1 Basic operations of A/D converter
Modification of description of setting methods and deletion of Caution 2 in 12.4.3 (1) A/D
conversion operation
Modification of Figure 13-1 Block Diagram of Operational Amplifier
Addition of Remark to Figure 13-2 Format of Operational Amplifier 0 Control Register
(AMP0M) (Products with Operational Amplifier Only)
Modification of Figure 13-4 Format of A/D Port Configuration Register 0 (ADPC0)
Modification of Figure 13-5 Format of A/D Port Configuration Register 1 (ADPC1) (78K0/KB2-
L and 78K0/KC2-L Only)
Modification of Table 13-2 Setting Functions of P10/ANI8/AMP1-, P12/ANI10/AMP1+ Pins
Modification of Table 13-4 Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+ Pins
Modification of Remark in Figure 14-4 Block Diagram of Serial Interface UART6
Addition of Note 3 to Figure 14-8 Format of Clock Selection Register 6 (CKSR6)
Modification of description in 14.3 (8) Port mode register 1 (PM1), port mode register 6 (PM6)
Modification of (1) 78K0/KY2-L and 78K0/KA2-L in Table 14-2 Relationship Between Register
Settings and Pins
Addition of 15.4.2 Setting transfer clock by using IICWL and IICWH registers
Modification of the mounted situation in the 78K0/KB2-L and 78K0/KC2-L
Modification of description in 16.3 (4) Port mode registers 1, 4, 6, 12 (PM1, PM4, PM6, PM12)
Modification of and addition of Notes 3 and 4 to Table 16-3 SO1n Output Status
Modification of maskable interrupts (internal) in the 78K0/KB2-L and 78K0/KC2-L
Modification of Table 17-1 Interrupt Source List (1/2)
Modification of Table 17-2 Flags Corresponding to Interrupt Request Sources (1/2)
Modification of Caution in Figure 17-4 Format of Interrupt Request Flag Registers (IF0L, IF0H,
IF1L, IF1H) (78K0/KB2-L) to Figure 17-6 Format of Interrupt Request Flag Registers (IF0L,
IF0H, IF1L, IF1H) (48-pin products of 78K0/KC2-L)
Modification of Caution in Figure 17-9 Format of Interrupt Mask Flag Registers (MK0L, MK0H,
MK1L, MK1H) (78K0/KB2-L) to Figure 17-11 Format of Interrupt Mask Flag Registers (MK0L,
MK0H, MK1L, MK1H) (48-pin products of 78K0/KC2-L)
Modification of Caution in Figure 17-14 Format of Priority Specification Flag Registers (PR0L,
PR0H, PR1L, PR1H) (78K0/KB2-L) to Figure 17-16 Format of Priority Specification Flag
Registers (PR0L, PR0H, PR1L, PR1H) (48-pin products of 78K0/KC2-L)
Addition of Caution 4 to 19.1.1 (2) STOP mode
Preliminary User’s Manual U19111EJ2V1UD
APPENDIX C REVISION HISTORY
Description
Classification
(b)
(a)
(a)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(3/5)
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