UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 733

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
p. 701
p. 702
p. 705
p. 706
CHAPTER 29 PACKAGE DRAWINGS
p. 707
CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS (PRELIMINARY)
p. 712
APPENDIX A DEVELOPMENT TOOLS
pp. 716 to
720
APPENDIX B REGISTER INDEX
p. 721
APPENDIX C REVISION HISTORY
p. 729
Remark “Classification” in the above table classifies revisions as follows.
Page
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
(3) Operational amplifier 0 in Analog Characteristics
(4) Operational amplifier 1 in Analog Characteristics
(7) LVI in Analog Characteristics
Flash Memory Programming Characteristics
Modification of 29.1 78K0/KY2-L
Addition of preliminary
Modification of URL of download site for development tools
Addition of chapter
Addition of chapter
Modification of V
Addition of phase margin and large-amplitude voltage gain (AV
Modification of gain-bandwidth product (GBW
Addition of phase margin and large-amplitude voltage gain (AV
Modification of gain-bandwidth product (GBW
Addition of supply voltage level (V
on (V
Modification of V
Modification of system clock frequency (f
Modification of Number of rewrites per chip (C
Addition of Note 1
DDLVI
)
DD
DD
range
range
Preliminary User’s Manual U19111EJ2V1UD
APPENDIX C REVISION HISTORY
LVI14
) and supply voltage when power supply voltage is turned
CLK
Description
)
OP0
OP1
erwr
)
)
)
OP0
OP1
)
)
Classification
(b)
(b)
(b)
(b)
(d)
(c)
(c)
(c)
(c)
(5/5)
733