R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 943

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.48 CAM Entry Table Busy Register (TSU_ADSBSY)
When CAM entry table registers (TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to
TSU_ADRL31) are set by register writing, the ADSBSY bit in this register is set to 1 (when the
process of reflecting the contents of the CAM entry table registers in the CAM controller is
completed inside the TSU, the ADSBSY bit is automatically restored to 0).
Access to TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31 is prohibited,
while the ADSBSY bit in this register is set to 1. This register is a read-only status register, which
must not be written to.
Bit
31 to 1
0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

ADSBSY
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
0
28
12


R
R
0
0
27
11


R
R
0
0
R/W Description
R
R
26
10


R
R
0
0
Reserved
These bits are always read as 0. The write value should
always be 0.
CAM Entry Table Setting Busy
When TSU_ADRH0 to TSU_ADRH31 and
TSU_ADRL0 to TSU_ADRL31 are set by register
writing, this bit is set to 1. When the process of
reflecting the contents of the CAM entry table registers
in the CAM controller is completed inside the TSU, this
bit is automatically restored to 0. Access to
TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to
TSU_ADRL31 is prohibited, while this bit is set to 1.
Writing to this register is also prohibited.
25

R

R
0
9
0
24

R

R
0
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
23


R
R
0
7
0
Rev. 2.00 May 22, 2009 Page 873 of 1982
22


R
R
0
6
0
21


R
R
0
5
0
20

R

R
0
4
0
19


R
R
0
3
0
REJ09B0256-0200
18


R
R
0
2
0
17


R
0
1
0
ADS
BSY
16

R
R
0
0
0