R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 896

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.12 Delayed Collision Detect Counter Register (CDCR)
CDCR is a 16-bit counter that indicates the number of all delayed collisions that occurred on the
line after the start of data transmission. When the value in this register reaches H'0000FFFF,
count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set
to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Rev. 2.00 May 22, 2009 Page 826 of 1982
REJ09B0256-0200
Bit
31 to 16
15 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

COSDC[15:0] All 0
R/W
31
15

R
0
0
R/W
30
14

R
0
0
R/W
29
13

R
0
0
Initial
Value
All 0
R/W
28
12

R
0
0
R/W
27
11

R
0
0
R/W
R
R/W
R/W
26
10

R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Delayed Collision Detect Count
These bits indicate the number of all delayed collisions
after the start of data transmission.
R/W
25

R
0
9
0
COSDC[15:0]
R/W
24

R
0
8
0
R/W
23

R
0
7
0
R/W
22

R
0
6
0
R/W
21

R
0
5
0
R/W
20

R
0
4
0
R/W
19

R
0
3
0
R/W
18

R
0
2
0
17

R
0
1
0
R/W
16

R
0
0
0