R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1146

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 27 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 May 22, 2009 Page 1076 of 1982
REJ09B0256-0200
Bit
6
5
Bit Name
RIE
TE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Interrupt Enable
Enables or disables generation of a receive-data-full
interrupt (RXI) request when the RDF flag or DR flag in
SCFSR is set to 1, a receive-error interrupt (ERI)
request when the ER flag in SCFSR is set to 1, and a
break interrupt (BRI) request when the BRK flag in
SCFSR or the ORER flag in SCLSR is set to 1.
0: Receive-data-full interrupt (RXI) request, receive-
1: Receive-data-full interrupt (RXI) request, receive-
Note: An RXI interrupt request can be cleared by
Transmit Enable
Enables or disables the start of serial transmission by
the SCIF.
Serial transmission is started when transmit data is
written to SCFTDR while the TE bit is set to 1.
0: Transmission disabled
1: Transmission enabled*
Note: SCSMR and SCFCR settings must be made, the
error interrupt (ERI) request, and break interrupt
(BRI) request disabled
error interrupt (ERI) request, and break interrupt
(BRI) request enabled
reading 1 from the RDF or DR flag, then clearing
the flag to 0, or by clearing the RIE bit to 0. ERI
and BRI interrupt requests can be cleared by
reading 1 from the ER, BRK, or ORER flag, then
clearing the flag to 0, or by clearing the RIE and
REIE bits to 0.
transmission format decided, and the transmit
FIFO reset, before the TE bit is set to 1.