R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1527

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 34 Serial Sound Interface (SSI)
When an underflow or overflow error condition is met, the CHNO[1:0] and SWNO bits can be
used to recover the SSI module to a known status. When an underflow or overflow occurs, the
host CPU can read the number of channels and the number of system words to determine what
point the serial audio stream has reached. In the transmitter case, the host CPU can skip forward
through the data it wants to transmit until it finds the sample data that matches what the SSI
module is expecting to transmit next, and so resynchronize with the audio data stream. In the
receiver case, the host CPU can skip forward storing null sample data until it is ready to store the
sample data that the SSI module is indicating that it will receive next to ensure consistency of the
number of received data, and so resynchronize with the audio data stream.
34.4.6
Serial Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode, then
the bit clock that is used in the shift register is derived from the SSI_SCK pin.
If the serial clock direction is set to output (SCKD = 1), the SSI Module is in clock master mode,
and the shift register uses the bit clock derived from the SSI_CLK input pin or its clock divided.
This input clock is then divided by the ratio in the serial oversampling clock division ratio
(CKDV) bit in SSICR and used as the bit clock in the shift register.
In either case, the SSI_SCK pin output is the same as the bit clock.
Rev. 2.00 May 22, 2009 Page 1457 of 1982
REJ09B0256-0200