R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 275

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

PURGE transaction: When the operand cache is enabled, the PURGE transaction checks the
operand cache and invalidates the hit entry. If the invalidated entry is dirty, the data is written back
to the external memory. If the transaction is not hit to the cache, it is no-operation.
FLUSH transaction: When the operand cache is enabled, the FLUSH transaction checks the
operand cache and if the hit line is dirty, then the data is written back to the external memory.
If the transaction is not hit to the cache or the hit entry is not dirty, it is no-operation.
7.5.2
This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a
cache miss. If it is known that a cache miss will result from a read or write operation, it is possible
to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss
due to the read or write operation, and so improve software performance. If a prefetch instruction
is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or
a protection violation, the result is no operation, and an exception is not generated. Details of the
prefetch instruction are given in the Programming Manual.
• Prefetch instruction (OC)
• Prefetch instruction (IC)
Prefetch Operation
: PREF @Rn
: PREFI @Rn
Rev. 2.00 May 22, 2009 Page 205 of 1982
Section 7 Caches
REJ09B0256-0200