R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 58

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 43.54 STIF Strobe Receive Timing............................................................................... 1880
Figure 43.55 STIF Strobe Transmit Timing ............................................................................. 1881
Figure 43.56 I
Figure 43.57 AC Characteristic Load Condition ...................................................................... 1883
Figure 43.58 SCIFn_SCK Input Clock Timing ........................................................................ 1884
Figure 43.59 SCIFn I/O Synchronous Mode Clock Timing..................................................... 1885
Figure 43.60 SIOF_MCLK Input Timing................................................................................. 1886
Figure 43.61 SIOF Transmission/Reception Timing
Figure 43.62 SIOF Transmission/Reception Timing
Figure 43.63 SIOF Transmission/Reception Timing
Figure 43.64 SIOF Transmission/Reception Timing
Figure 43.65 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) .............. 1889
Figure 43.66 SIM Module Signal Timing ................................................................................ 1890
Figure 43.67 MMCIF Transmit Timing ................................................................................... 1891
Figure 43.68 MMCIF Receive Timing (Sampling at the Rising Edge) .................................... 1892
Figure 43.69 HAC Cold Reset Timing ..................................................................................... 1893
Figure 43.70 HAC SYNC Output Timing ................................................................................ 1893
Figure 43.71 HAC Clock Input Timing.................................................................................... 1894
Figure 43.72 HAC Interface Module Signal Timing ................................................................ 1894
Figure 43.73 SSI Clock Input/Output Timing .......................................................................... 1895
Figure 43.74 SSI Transmit Timing (1) ..................................................................................... 1895
Figure 43.75 SSI Transmit Timing (2) ..................................................................................... 1896
Figure 43.76 SSI Receive Timing (1)....................................................................................... 1896
Figure 43.77 SSI Receive Timing (2)....................................................................................... 1896
Figure 43.78 USB Clock Timing.............................................................................................. 1897
Figure 43.79 LCDC Module Signal Timing ............................................................................. 1899
Figure 43.80 GPIO Timing....................................................................................................... 1899
Figure 43.81 TCK Input Timing............................................................................................... 1900
Figure 43.82 PRESET Hold Timing......................................................................................... 1901
Figure 43.83 H-UDI Data Transfer Timing.............................................................................. 1901
Figure 43.84 ASEBRK Pin Break Timing................................................................................ 1901
Figure 43.85 Output Load Circuit ............................................................................................ 1903
Figure 43.86 Load Capacitance - Delay Time .......................................................................... 1904
Appendix
Figure B.1 Instruction Prefetch................................................................................................. 1907
Figure D.1 Schematic Diagram of External Circuits ................................................................ 1910
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(Master Mode 1, Sampling at the Falling Edge).................................................. 1887
(Master Mode 1, Sampling at the Rising Edge)................................................... 1887
(Master Mode 2, Sampling at the Falling Edge).................................................. 1888
(Master Mode 2, Sampling at the Rising Edge)................................................... 1888
2
C Bus Interface Input/Output Timing ............................................................... 1883