R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 634

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 PCI Controller (PCIC)
13.5
13.5.1
When the PCIC is used in target mode and all the three conditions below are satisfied, data may be
lost during a PCIC target read.
1. PFCS bit in PCICR = 1 (32-byte pre-fetch enabled)
2. FTO bit in PCICR = 1 (TRDY control enabled)
3. PFE bit in PCICR = 1 (pre-fetch enabled)
For target reading in target mode, at least one of the above three conditions must be cancelled.
13.5.2
When the PCIC is used while all the five conditions below are satisfied, REQn (n = 3 to 1) with
the lowest priority is masked, thus disabling correct transfers via the PCI bus, which leads to
unstable operation of the PCI bus system.
1. Host mode (MD6 = high)
2. PCI bus master arbitration mode is set to fixed mode (BMAM bit in PCICR = 0)
3. In addition to this LSI (with the PCIC in host mode), two or more external PCI devices that
4. Among the above external devices, there is at least one device (REQm) that does not execute
5. There is an external device (REQn; n > m) that can be a bus master with a priority lower than
Rev. 2.00 May 22, 2009 Page 564 of 1982
REJ09B0256-0200
Figure 13.27 Timing Example of Device (REQm) Not Executing REQ Negation and FRAME
can be a bus master are connected to the PCI bus.
REQ negation and FRAME assertion simultaneously when a single transaction is requested
(single or burst transfer).
the priority of the external device (REQm) satisfying condition 4 above.
Usage Notes
Notes on PCIC Target Reading
Notes on Host Mode
PCICLK
REQm
GNTm
FRAME
Assertion Simultaneously