R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1977

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

B.
This LSI is provided with an internal buffer for holding pre-read instructions, and always performs
pre-reading. Therefore, program code must not be located in the last 64-byte area of any memory
space. If program code is located in these areas, a bus access for instruction prefetch may occur
exceeding the memory areas boundary. A case in which this is a problem is shown below.
Figure B.1 presupposes a case in which the instruction (ADD) indicated by the program counter
(PC) and the address H'04000002 instruction prefetch are executed simultaneously. It is also
assumed that the program branches to an area other than area 1 after executing the following JMP
instruction and delay slot instruction.
In this case, a bus access (instruction prefetch) to area 1 may unintentionally occur from the
programming flow.
Instruction Prefetch Side Effects:
1. It is possible that an external bus access caused by an instruction prefetch may result in
2. If there is no device to reply to an external bus request caused by an instruction prefetch, hang-
Remedies:
1. These illegal instruction fetches can be avoided by using the MMU.
2. The problem can be avoided by not locating program code in the last 64 bytes of any area.
misoperation of an external device, such as a FIFO, connected to the area concerned.
up will occur.
Instruction Prefetching and Its Side Effects
Area 0
Area 1
Address
H'03FF FFF8
H'03FF FFFA
H'03FF FFFC
H'03FF FFFE
H'4000 0000
H'4000 0002
:
Figure B.1 Instruction Prefetch
Instruction
ADD R1,R4
JMP @R2
NOP
NOP
:
Rev. 2.00 May 22, 2009 Page 1907 of 1982
PC (Program Counter)
Instruction prefetch address
REJ09B0256-0200
Appendix