R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1229

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(2)
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A
bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source
selection, see Table 28.5.
When an external clock is input at the SCIF_SCK pin, the clock frequency should be 16 times the
bit rate used.
When the SCIF is operated on an internal clock, a clock whose frequency is 16 times the bit rate is
output from the SCIF_SCK pin.
(3)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0,
then initialize the SCIF as described below.
When the operating mode or transfer format, etc., is changed, the TE and RE bits must be cleared
to 0 before making the change using the following procedure.
1. When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the TE and RE bits to
2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in
3. When an external clock is used the clock should not be stopped during operation, including
0 does not change the contents of SCFSR, SCFTDR, or SCFRDR.
SCFSR has been set. TEND can also be cleared to 0 during transmission, but the data being
transmitted will go to the mark state after the clearance. Before setting TE again to start
transmission, the TFRST bit in SCFCR should first be set to 1 to reset SCFTDR.
initialization, since operation will be unreliable in this case.
Clock
SCIF Initialization (Asynchronous Mode)
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Rev. 2.00 May 22, 2009 Page 1159 of 1982
REJ09B0256-0200