R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 649

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
27 to 25
24
23
22
21
Bit Name
RPT[2:0]
—
DO
—
DVMD
Initial
Value
000
0
0
0
0
R/W
R/W
R
R/W
R
R/W
Descriptions
DMA Setting Renewal Specify
These bits are enabled in CHCR0 to CHCR3.
000: Normal mode
001: Repeat mode
010: Repeat mode
011: Repeat mode
100: Reserved (setting prohibited)
101: Reload mode
110: Reload mode
111: Reload mode
Reserved
This bit is always read as 0. The write value should
always be 0.
DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR0 to CHCR3.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
Reserved
This bit is always read as 0. The write value should
always be 0.
Division Transfer Mode Specification
Specifies the execution of the DMA transfer in 16-byte
units between the on-chip peripheral module STIF and
the external memory.
When the STIF is used, always write 1 to this bit. When
the STIF is not used, always write 0 to this bit.
SAR/DAR/TCR used as repeat area
DAR/TCR used as repeat area
SAR/TCR used as repeat mode
SAR/DAR/TCR used as reload area
DAR/TCR used as reload area
SAR/TCR used as reload area
Section 14 Direct Memory Access Controller (DMAC)
Rev. 2.00 May 22, 2009 Page 579 of 1982
REJ09B0256-0200