R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1231

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(4)
Figure 28.7 shows a sample flowchart for serial transmission.
Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Serial Data Transmission (Asynchronous Mode):
Write transmit data in SCFTDR
Clear TE bit in SCSCR to 0
Read TEND flag in SCFSR
Read TDFE flag in SCFSR
Clear SPB2DT to 0 and
Start of transmission
All data transmitted?
End of transmission
set SPB2IO to 1
Break output?
TEND = 1?
TDFE = 1?
Yes
Yes
Yes
Yes
Figure 28.7 Sample Serial Transmission Flowchart
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
No
No
No
No
[1]
[2]
[3]
[1] SCIF status check and transmit data write:
[2] Serial transmission continuation procedure:
[3] Break output at the end of serial transmission:
Read SCFSR and check that the TDFE flag is set to 1,
then write transmit data to SCFTDR, and clear the TDFE
and TEND flags to 0.
The number of transmit data bytes that can be written is
16 - (transmit trigger set number).
To continue serial transmission, read 1 from the TDFE flag
to confirm that writing is possible, then write data to SCFTDR,
and then clear the TDFE flag to 0.
To output a break in serial transmission, clear the SPB2DT
bit to 0 and set the SPB2IO bit to 1 in SCSPTR, then clear
the TE bit in SCSCR to 0.
In [1] and [2], it is possible to ascertain the number of data
bytes that can be written from the number of transmit data
bytes in SCFTDR indicated by SCFDR.
Rev. 2.00 May 22, 2009 Page 1161 of 1982
REJ09B0256-0200

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