R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet
R5S77631Y266BGV
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R5S77631Y266BGV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH7763 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH SH-4A Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring ...
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Rev. 2.00 May 22, 2009 Page ii of lxviii ...
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Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be ...
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Abbreviations ALU Arithmetic Logic Unit ASID Address Space Identifier BGA Ball Grid Array CMT Timer/Counter (Compare Match Timer) CPG Clock Pulse Generator CPU Central Processing Unit DDR Double Data Rate DDRIF DDR-SDRAM Interface DMA Direct Memory Access DMAC Direct Memory ...
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MSB Most Significant Bit PC Program Counter PCI Peripheral Component Interconnect PCIC PCI (local bus) Controller PFC Pin Function Controller RISC Reduced Instruction Set Computer RTC Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO SSI ...
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Section 1 Overview................................................................................................1 1.1 Features of the SH7763.......................................................................................................... 1 1.2 Block Diagram ..................................................................................................................... 13 1.3 Pin Arrangement .................................................................................................................. 14 Section 2 Programming Model ............................................................................37 2.1 Data Formats........................................................................................................................ 37 2.2 Register Descriptions ........................................................................................................... 38 2.2.1 Privileged Mode and Banks .................................................................................... 38 ...
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Exception Handling Functions........................................................................................... 109 5.3.1 Exception Handling Flow ..................................................................................... 109 5.3.2 Exception Handling Vector Addresses ................................................................. 109 5.4 Exception Types and Priorities .......................................................................................... 110 5.5 Exception Flow .................................................................................................................. 112 5.5.1 Exception Flow..................................................................................................... 112 5.5.2 Exception Source Acceptance............................................................................... 114 5.5.3 ...
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Instruction TLB Protection Violation Exception .................................................. 168 6.5.4 Data TLB Multiple Hit Exception ........................................................................ 169 6.5.5 Data TLB Miss Exception .................................................................................... 169 6.5.6 Data TLB Protection Violation Exception............................................................ 170 6.5.7 Initial Page Write Exception................................................................................. 171 6.6 Memory-Mapped TLB Configuration................................................................................ ...
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Memory-Mapped Cache Configuration ............................................................................. 206 7.6.1 IC Address Array.................................................................................................. 206 7.6.2 IC Data Array ....................................................................................................... 208 7.6.3 OC Address Array ................................................................................................ 209 7.6.4 OC Data Array...................................................................................................... 210 7.7 Store Queues ...................................................................................................................... 212 7.7.1 SQ Configuration.................................................................................................. 212 7.7.2 Writing to ...
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Interrupt Priority Register (INTPRI)..................................................................... 249 9.3.4 Interrupt Source Register (INTREQ).................................................................... 250 9.3.5 Interrupt Mask Register 0 (INTMSK0) ................................................................ 251 9.3.6 Interrupt mask register 1 (INTMSK1) .................................................................. 253 9.3.7 Interrupt mask register 2 (INTMSK2) .................................................................. 254 9.3.8 Interrupt Mask Clear ...
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Section 10 SuperHyway Bus Bridge (SBR)...................................................... 313 10.1 Features.............................................................................................................................. 313 10.2 Register Descriptions......................................................................................................... 314 10.2.1 Bus Arbitration Priority Level Setting Register (SBRIVCLV) ............................ 315 10.2.2 SuperHyway Bus Priority Control Resister (PRPRICR) ...................................... 316 10.3 Operation ........................................................................................................................... 317 10.3.1 SuperHyway Bus ...
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Data Alignment..................................................................................................... 414 12.3.2 Data Alignment in Peripheral Modules ................................................................ 416 12.4 Register Descriptions ......................................................................................................... 417 12.4.1 Memory Interface Mode Register (MIM) ............................................................. 419 12.4.2 DDR-SDRAM Control Register (SCR)................................................................ 423 12.4.3 DDR-SDRAM Timing Register (STR)................................................................. 425 12.4.4 DDR-SDRAM Row ...
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Power Management .............................................................................................. 551 13.4.8 PCI Local Bus Basic Interface.............................................................................. 552 13.5 Usage Notes ....................................................................................................................... 564 13.5.1 Notes on PCIC Target Reading............................................................................. 564 13.5.2 Notes on Host Mode ............................................................................................. 564 Section 14 Direct Memory Access Controller (DMAC)................................... 567 14.1 ...
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Register Descriptions ......................................................................................................... 625 15.3.1 External CPU Control Register (EXCCTRL) ....................................................... 626 15.3.2 External CPU Memory Space Select Register (EXCMSETR) ............................. 627 15.3.3 External CPU Interrupt Output Control Register (EXCINOR)............................. 628 15.4 Operation ........................................................................................................................... 629 Section 16 Clock Pulse ...
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Standby Control Register (STBCR)...................................................................... 673 18.3.2 Module Stop Register 0 (MSTPCR0) ................................................................... 674 18.3.3 Module Stop Register 1 (MSTPCR1) ................................................................... 675 18.4 Sleep Mode ........................................................................................................................ 680 18.4.1 Transition to Sleep Mode...................................................................................... 680 18.4.2 Canceling Sleep Mode .......................................................................................... 680 18.5 ...
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Section 20 16-Bit Timer Pulse Unit (TPU) .......................................................709 20.1 Features.............................................................................................................................. 709 20.2 Input/Output Pins ............................................................................................................... 712 20.3 Register Descriptions ......................................................................................................... 713 20.3.1 Timer Control Registers (TCR) ............................................................................ 717 20.3.2 Timer Mode Registers (TMDR) ........................................................................... 721 20.3.3 Timer I/O Control Registers ...
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Hz Counter (R64CNT)..................................................................................... 766 22.4.2 Second Counter (RSECCNT) ............................................................................... 766 22.4.3 Minute Counter (RMINCNT)............................................................................... 767 22.4.4 Hour Counter (RHRCNT) .................................................................................... 767 22.4.5 Day-of-Week Counter (RWKCNT)...................................................................... 768 22.4.6 Day Counter (RDAYCNT)................................................................................... 769 22.4.7 Month Counter (RMONCNT) .............................................................................. 770 22.4.8 ...
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PHY_INT Polarity Register (PIPR)...................................................................... 824 23.3.11 Transmit Retry Over Counter Register (TROCR) ................................................ 825 23.3.12 Delayed Collision Detect Counter Register (CDCR)............................................ 826 23.3.13 Lost Carrier Counter Register (LCCR)................................................................. 827 23.3.14 CRC Error Frame Receive Counter Register (CEFCR)........................................ 828 23.3.15 ...
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CAM Entry Table POST1 Register (TSU_POST1).............................................. 879 23.3.51 CAM Entry Table POST2 Register (TSU_POST2).............................................. 882 23.3.52 CAM Entry Table POST3 Register (TSU_POST3).............................................. 885 23.3.53 CAM Entry Table POST4 Register (TSU_POST4).............................................. 888 23.3.54 CAM Entry Table 0H to 31H Registers ...
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Transmit FIFO Threshold Register (TFTR).......................................................... 926 23.3.79 FIFO Depth Register (FDR) ................................................................................. 927 23.3.80 Receiving Method Control Register (RMCR) ...................................................... 928 23.3.81 Receive Descriptor Fetch Address Register (RDFAR)......................................... 929 23.3.82 Receive Descriptor Finished Address Register (RDFXR) .................................... 930 23.3.83 ...
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Register Descriptions....................................................................................................... 1002 25.3.1 Mode Registers 0, 1 (STIMDR0, STIMDR1)..................................................... 1004 25.3.2 Control Registers 0, 1 (STICR0, STICR1) ......................................................... 1008 25.3.3 Interrupt Status Registers 0, 1 (STIISR0, STIISR1) ........................................... 1009 25.3.4 Interrupt Enable Registers 0, 1 (STIIER0, STIIER1) ......................................... ...
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Master Receiver .................................................................................................. 1057 26.5.3 Master Transmitter—Restart—Master Receiver ................................................ 1058 Section 27 Serial Communication Interface with FIFO (SCIF) ......................1061 27.1 Features............................................................................................................................ 1061 27.2 Input/Output Pins ............................................................................................................. 1067 27.3 Register Descriptions ....................................................................................................... 1068 27.3.1 Receive Shift Register (SCRSR)......................................................................... 1070 27.3.2 ...
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Bit Rate Register (SCBRR) ................................................................................ 1143 28.3.9 FIFO Control Register (SCFCR) ........................................................................ 1144 28.3.10 FIFO Data Count Register (SCFDR).................................................................. 1146 28.3.11 Serial Port Register (SCSPTR) ........................................................................... 1147 28.3.12 Line Status Register (SCLSR) ............................................................................ 1149 28.3.13 BRG Frequency Division Register ...
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Serial Timing ...................................................................................................... 1220 29.4.3 Transfer Data Format.......................................................................................... 1222 29.4.4 Register Allocation of Transfer Data .................................................................. 1224 29.4.5 Control Data Interface ........................................................................................ 1227 29.4.6 FIFO.................................................................................................................... 1229 29.4.7 Transmit and Receive Procedures....................................................................... 1231 29.4.8 Interrupts............................................................................................................. 1236 29.4.9 Transmit and Receive ...
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Transfer Byte Number Count Register (TBCR) ................................................. 1299 31.3.4 Transfer Block Number Counter (TBNCR)........................................................ 1300 31.3.5 Command Registers (CMDR0 to CMDR5).............................................. 1300 31.3.6 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD)............................ 1302 31.3.7 Command ...
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PC Card Interface Timing................................................................................... 1386 32.5 Usage Notes ..................................................................................................................... 1391 Section 33 Audio Codec Interface (HAC) .......................................................1393 33.1 Features............................................................................................................................ 1393 33.2 Input/Output Pins ............................................................................................................. 1394 33.3 Register Descriptions ....................................................................................................... 1395 33.3.1 Control and Status Register (HACCR) ............................................................... 1396 33.3.2 ...
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Receive Operation .............................................................................................. 1454 34.4.6 Serial Clock Control ........................................................................................... 1457 34.5 Usage Note....................................................................................................................... 1458 34.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation .......... 1458 34.5.2 Restrictions for Operation in Slave Mode........................................................... 1458 Section 35 USB Host Controller ...
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Issuing USB Bus Reset ....................................................................................... 1495 Section 36 USB Function Controller (USBF) .................................................1497 36.1 Features............................................................................................................................ 1497 36.2 Input/Output Pins ............................................................................................................. 1499 36.3 Register Descriptions ....................................................................................................... 1500 36.3.1 Interrupt Flag Register 0 (IFR0) ......................................................................... 1506 36.3.2 Interrupt Flag Register 1 ...
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Time Stamp Register (TSRH/TSRL).................................................................. 1546 36.3.36 Control Register 0 (CTLR0) ............................................................................... 1548 36.3.37 Control Register 1 (CTLR1) ............................................................................... 1550 36.3.38 Endpoint Information Register (EPIR) ............................................................... 1551 36.3.39 Timer Register (TMRH/TMRL) ......................................................................... 1557 36.3.40 Set Time Out Register (STOH/STOL) ............................................................... ...
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LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ......... 1604 37.3.8 LCDC Palette Control Register (LDPALCR)..................................................... 1605 37.3.9 Palette Data Registers (LDPR00 to LDPRFF) ..................................... 1606 37.3.10 LCDC Horizontal Character Number Register (LDHCNR) ............................... ...
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Scan Mode (MDS1 = 1, MDS0 = 1) ................................................................... 1668 38.4.4 A/D Conversion Time......................................................................................... 1670 38.5 Interrupts.......................................................................................................................... 1670 38.6 Definitions of A/D Conversion Accuracy........................................................................ 1671 38.7 Usage Notes ..................................................................................................................... 1673 38.7.1 Setting Analog Input Voltage ............................................................................. 1673 38.7.2 Processing ...
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Port D Data Register (PDDR)............................................................................. 1726 40.2.20 Port E Data Register (PEDR).............................................................................. 1727 40.2.21 Port F Data Register (PFDR) .............................................................................. 1728 40.2.22 Port G Data Register (PGDR)............................................................................. 1729 40.2.23 Port H Data Register (PHDR)............................................................................. 1730 40.2.24 Port I Data ...
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Channel Match Flag Register (CCMFR) ............................................................ 1781 41.2.9 Break Control Register (CBCR) ......................................................................... 1782 41.3 Operation Description...................................................................................................... 1783 41.3.1 Definition of Words Related to Accesses ........................................................... 1783 41.3.2 User Break Operation Sequence ......................................................................... 1784 41.3.3 Instruction Fetch Cycle Break ...
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AC Characteristics ........................................................................................................... 1835 43.4.1 Clock and Control Signal Timing ....................................................................... 1836 43.4.2 Control Signal Timing ........................................................................................ 1840 43.4.3 Bus Timing ......................................................................................................... 1842 43.4.4 DDRIF Signal Timing ........................................................................................ 1860 43.4.5 INTC Module Signal Timing.............................................................................. 1863 43.4.6 External CPU Interface ...
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J. Heat Radiation ................................................................................................................. 1947 J.1 Heat Resistance Simulation Conditions.............................................................. 1947 J.2 Analysis Results of Heat Resistance Simulation ................................................ 1948 Main Revisions and Additions in this Edition................................................... 1951 Index ....................................................................................................... 1971 Rev. 2.00 May 22, 2009 Page xxxviii of lxviii ...
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Section 1 Overview Figure 1.1 SH7763 Block Diagram .............................................................................................. 13 Figure 1.2 Pin Arrangement.......................................................................................................... 15 Section 2 Programming Model Figure 2.1 Data Formats ............................................................................................................... 37 Figure 2.2 CPU Register Configuration in Each Processing Mode .............................................. 41 Figure 2.3 General Registers ...
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Figure 6.9 Flowchart of Memory Access Using UTLB.............................................................. 160 Figure 6.10 Flowchart of Memory Access Using ITLB ............................................................. 161 Figure 6.11 Operation of LDTLB Instruction............................................................................. 164 Figure 6.12 Memory-Mapped ITLB Address Array................................................................... 173 Figure 6.13 Memory-Mapped ITLB Data Array ........................................................................ ...
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Figure 11.7 Example of 16-Bit Data-Width SRAM Connection ................................................ 369 Figure 11.8 Example of 8-Bit Data-Width SRAM Connection .................................................. 369 Figure 11.9 SRAM Interface Wait Timing (Software Wait Only) ............................................. 370 Figure 11.10 SRAM Interface Wait Cycle Timing (Wait Cycle ...
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Figure 11.38 Byte-Control SRAM Basic Read Cycle (One Internal Wait + One External Wait).............................................................. 403 Figure 11.39 Wait Cycles between Access Cycles ..................................................................... 405 Figure 11.40 Arbitration Sequence............................................................................................. 407 Section 12 DDR-SDRAM Interface (DDRIF) Figure 12.1 DDRIF Block Diagram ........................................................................................... ...
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Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local bus (Byte Swapping: TBS = 1) ...................................................................................... 538 Figure 13.9 PCI local bus to SuperHyway bus Memory Map .................................................... 539 Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation ...
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Figure 14.11 DMA Transfer Flowchart...................................................................................... 609 Figure 14.12 Reload Mode Transfer........................................................................................... 611 Figure 14.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 612 Figure 14.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 612 ...
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Figure 18.4 STATUS Output when an Interrupt Occurs in Sleep Mode .................................... 687 Section 19 Timer Unit (TMU) Figure 19.1 Block Diagram of TMU .......................................................................................... 690 Figure 19.2 Example of Count Operation Setting Procedure ..................................................... 702 Figure 19.3 TCNT Auto-Reload ...
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Figure 22.4 Example of Use of Alarm Function......................................................................... 782 Figure 22.5 Example of Crystal Oscillator Circuit Connection.................................................. 784 Section 23 Gigabit Ethernet Controller (GETHER) Figure 23.1 Configuration of GETHER ..................................................................................... 786 Figure 23.2 GETHER Data Path and Various Settings .............................................................. ...
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Figure 23.36 Independent Bus Release Flowchart (IDLE in Write in Figure 23.33) ................. 993 Figure 23.37 MII-RMII Conversion Circuit ............................................................................... 994 Figure 23.38 Data Subject to Checksum Calculation ................................................................. 995 Section 25 Stream Interface (STIF) Figure 25.1 Block Diagram of ...
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Figure 27.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ................................................ 1105 Figure 27.14 Sample Operation Using Modem Control (SCIF0_RTS) (Only in Channel 0) ............................................................................................. 1106 Figure 27.15 Data Format in Clocked Synchronous Communication ...................................... 1106 ...
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Figure 28.23 BRG Block Diagram ........................................................................................... 1183 Section 29 Serial I/O with FIFO (SIOF) Figure 29.1 Block Diagram of SIOF ........................................................................................ 1188 Figure 29.2 Serial Clock Supply............................................................................................... 1219 Figure 29.3 Serial Data Synchronization Timing ..................................................................... 1221 Figure 29.4 SIOF Transmit/Receive ...
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Section 31 Multimedia Card Interface (MMCIF) Figure 31.1 MMCIF Block Diagram ........................................................................................ 1288 Figure 31.2 Example of Command Sequence for Commands Not Requiring Command Response................................................................................................................ 1330 Figure 31.3 Example of Operational Flow for Commands Not Requiring Command Response ............................................................................................................... 1331 ...
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Figure 31.18 (1) Example of Operational Flow for Commands with Write Data (Pre-defined Multiblock Transfer)................................................................. 1351 Figure 31.18 (2) Example of Operational Flow for Commands with Write Data (Pre-defined Multiblock Transfer)................................................................. 1352 Figure 31.19 (1) Example of Operational Flow for ...
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Figure 34.8 Multichannel Format (4 Channels, with Padding Bits First, Followed by Serial Data, with Padding) .... 1445 Figure 34.9 Basic Sample Format (Transmit Mode with Example System/Data Word Length)................................. 1446 Figure 34.10 Inverted Clock ..................................................................................................... 1447 Figure 34.11 Inverted ...
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Figure 36.19 Example of Transceiver Connection for USB function Controller ..................... 1583 Figure 36.20 Set Timing of TR Interrupt Flag.......................................................................... 1586 Section 37 LCD Controller (LCDC) Figure 37.1 LCDC Block Diagram........................................................................................... 1588 Figure 37.2 Valid Display and the Retrace Period.................................................................... ...
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Figure 38.4 Example of A/D Converter Operation (Scan Mode, Three Channels AN0 to AN2 Selected) ........................................... 1669 Figure 38.5 Definitions of A/D Conversion Accuracy ............................................................. 1672 Figure 38.6 Example of Analog Input Pin Protection Circuit................................................... 1673 Section 39 D/A Converter ...
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Figure 43.17 Burst ROM Bus Cycle (No Wait, No Address Setup/Hold Time Insertion, RDS = 1, RDH = 0)............ 1849 Figure 43.18 Burst ROM Bus Cycle (One Wait by Software + One Wait by RDY)................ 1850 Figure 43.19 PCMCIA Memory ...
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Figure 43.54 STIF Strobe Receive Timing............................................................................... 1880 Figure 43.55 STIF Strobe Transmit Timing ............................................................................. 1881 2 Figure 43. Bus Interface Input/Output Timing ............................................................... 1883 Figure 43.57 AC Characteristic Load Condition ...................................................................... 1883 Figure 43.58 SCIFn_SCK Input Clock Timing ...
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Figure E.1 Connection Example of Bypass Capacitors for Analog Power Supply................... 1913 Figure F.1 Package Dimensions (449-Pin) ............................................................................... 1914 Figure J.1 Overall View of Simulation Model (with heat sink)................................................ 1948 Figure J.2 Heat Sink Model ...................................................................................................... 1949 Rev. 2.00 May ...
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Rev. 2.00 May 22, 2009 Page lviii of lxviii ...
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Section 1 Overview Table 1.1 Features of the SH7763............................................................................................. 2 Table 1.2 Pin Configuration.................................................................................................... 16 Section 2 Programming Model Table 2.1 Initial Register Values............................................................................................. 40 Table 2.2 Bit Allocation for FPU Exception Handling........................................................... 50 Section 3 Instruction Set Table 3.1 ...
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Section 7 Caches Table 7.1 Cache Features...................................................................................................... 187 Table 7.2 Store Queue Features ............................................................................................ 187 Table 7.3 Register Configuration.......................................................................................... 190 Table 7.4 Register States in Each Processing State .............................................................. 190 Section 8 L Memory Table 8.1 L Memory Addresses............................................................................................ 217 ...
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Table 11.15 Relationship between Address and CE When Using PCMCIA Interface ......... 379 Section 12 DDR-SDRAM Interface (DDRIF) Table 12.1 Pin Configuration.................................................................................................. 413 Table 12.2 Access and Data Alignment in Little Endian Mode (External Bus Width is 32 Bits) ............................................................................ ...
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Table 15.4 Access and Data Alignment for Little Endian ...................................................... 630 Table 15.5 Access and Data Alignment for Big Endian ......................................................... 631 Section 16 Clock Pulse Generator (CPG) Table 16.1 Pin Configuration and Functions of CPG ............................................................. 638 Table 16.2 ...
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Table 20.13 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 747 Section 21 Compare Match Timer (CMT) Table 21.1 Register Configuration.......................................................................................... 751 Table 21.2 Register State in Each Operating Mode ................................................................ 752 Section 22 Realtime Clock (RTC) Table 22.1 RTC Pins............................................................................................................... ...
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA) Table 28.1 Pin Configuration................................................................................................ 1125 Table 28.2 Register Configuration........................................................................................ 1126 Table 28.3 Register States in each Operation Mode ............................................................. 1127 Table 28.4 SCSMR Settings ................................................................................................. 1143 Table 28.5 Baud Rate (3.6864 ...
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Table 31.6 Correspondence between Command Response Byte Number and RSPR........... 1302 Table 31.7 List of Chattering Elimination Pulse Cycles....................................................... 1327 Table 31.8 MMCIF Interrupt Sources................................................................................... 1359 Section 32 PC Card Controller (PCC) Table 32.1 Features of the PCMCIA Interface ..................................................................... ...
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Table 37.3 Register State in Each Operating Mode.............................................................. 1591 Table 37.4 I/O Clock Frequency and Clock Division Ratio ................................................. 1594 Table 37.5 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (32-bit SDRAM) .................................................................................. 1627 Table 37.6 ...
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Section 43 Electrical Characteristics Table 43.1 Absolute Maximum Ratings ............................................................................... 1827 Table 43.2 Power-On and Power-Off Timing....................................................................... 1829 Table 43.3 DC Characteristics (1) [common] ....................................................................... 1831 Table 43.4 DC Characteristics (2-a) [Except of USB Transceiver and I Table 43.5 DC ...
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Table 43.40 D/A Converter Characteristics........................................................................ 1902 Appendix Table D.1 Mode Control Pins.............................................................................................. 1909 Table G.1 Pin States ............................................................................................................ 1915 Table H.1 Handling of Unused Pins .................................................................................... 1933 Table I.1 Register Configuration........................................................................................ 1945 Table J.1 Heat Resistance Simulation Results.................................................................... 1948 Rev. ...
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Features of the SH7763 This LSI is a single-chip multifunction CMOS microcomputer that integrates the Renesas Technology original RISC (reduced instruction set computer) CPU core with the peripheral functions required for a wide range of application systems such as ...
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Section 1 Overview Table 1.1 Features of the SH7763 Item Features • Maximum operating 266 MHz frequency • Performance 478 MIPS (266 MHz), 1862 MFLOPS (266 MHz) • CPU Renesas Technology original architecture • 32-bit internal data bus • General-register ...
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Item Features • FPU On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation ...
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Section 1 Overview Item Features • Memory 4 Gbytes of physical address space, 256 address spaces (identified by management an 8-bit ASID (address space identifier)) unit (MMU) • Supports single virtual memory mode and multiple virtual memory mode • Supports ...
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Item Features • Clock pulse Selectable CPU clock: 8 times EXTAL generator (CPG) • Clock modes: CPU frequency: Local bus frequency: DDR-SDRAM I/F frequency: 1/2 times the CPU clock Peripheral bus 0 frequency: 1/4 times the ...
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Section 1 Overview Item Features • Local bus state Physical address space divided into seven areas (areas 0 to 6), each controller (LBSC) comprising Mbytes I/F configuration, bus width, and wait cycle insertion are settable for ...
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Item Features • DDR-SDRAM DDR-SDRAM interface: 32-bit data bus width controller (DDRIF) • Supports the DDR266 or DDR200 SDRAM • DDR-SDRAM refreshing Programmable refreshing intervals (auto-refresh mode) Self-refresh mode • Supports a burst length of 2 • Switching ...
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Section 1 Overview Item Features • Timer unit (TMU) 6-channel auto-reload 32-bit timer • Input-capture function (channel 2 only) • For channels choice of six types of counter input clock for each channel Five peripheral clocks ...
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Item Features • Multimedia card Supports MMC mode interface (MMCIF) • A maximum bit rate of 16.7 Mbps at 33 MHz of peripheral clock 1 • Interface is through the CLK output pin for transfer clock output, CMD I/O pin ...
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Section 1 Overview Item Features • 10 bits ± 4LSB, four channels A/D converter • Conversion time: 8.5 µs (ADC) • Three conversion modes: single mode, multi-mode, and scan mode • Four data registers • Sample-and-hold function • Generates A/D ...
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Item Features • Stream interface Parallel connection available when MPEG2 TS stream is input (STIF) Parallel stream connection Stream input: Master mode with clock-valid operation Byte transfer mode with strobe operation Stream output: Master mode with clock-valid ...
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Section 1 Overview Item Features • Security Encryption/decryption based on AES (Advanced Encryption Standard) 1 accelerator* (Key length: 128, 192, and 256 bits) (SECURITY) • DES/Triple-DES encryption/decryption based on DES (Data Encryption Standard) • Hash function generation based on the ...
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Block Diagram CPU FPU UBC AUD SECURITY* GETHER USBH USBF [Legend] AUD: Advanced user debugger CMT: Compare match timer CPG: Clock pulse generator CPU: Central processing unit DDRIF: DDR-SDRAM interface DMAC: Direct memory access controller FPU: Floating-point unit GPIO: ...
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Section 1 Overview 1.3 Pin Arrangement Figure 1.2 shows the pin arrangement and table 1.2 lists the pin configuration of this LSI. Rev. 2.00 May 22, 2009 Page 14 of 1982 REJ09B0256-0200 ...
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Figure 1.2 Pin Arrangement Rev. 2.00 May 22, 2009 Page 15 of 1982 Section 1 Overview REJ09B0256-0200 ...
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Section 1 Overview Table 1.2 Pin Configuration Pin No. Pin Name A1 VSSQ-DDR A2 VCCQ-DDR A3 M_VREF A4 M_CLK0 M_CLK1 A5 M_WE A6 M_RAS A7 A8 M_BA0 A9 M_A10 A10 M_A1 A11 M_A3 A12 XTAL2 A13 USBM A14 PTI2/ST0M_STARTI/IIC0_SCL/ SIOF1_RXD/USB_OVRCRT/ ...
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Pin No. Pin Name A19 PTJ1/ST0M_CLKIO/ RMII1_RX_ER/LCD_CLK CS5/CE1A A20 A21 PTM6/D30/EX_AD30/ST0_D6/ ET0_RX-CLK/RMII0_TXD1/ PINT6 A22 PTM4/D28/EX_AD28/ST0_D4/ ET0_PHY-INT/RMII0_RXD0/ PINT4 CS0 A23 A24 VSSQ A25 VSSQ B1 VCCQ-DDR B2 VSSQ-DDR M_BKPRST B3 B4 M_CKE B5 M_A13 M_CAS B6 M_CS B7 B8 M_BA1 B9 ...
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Section 1 Overview Pin No. Pin Name B14 PTI3/ST0M_VALIDI/IIC0_SDA/ SIOF1_MCLK/USB_CLK B15 PTK7/ST1_D7/GET0_ERXD7/ SIOF2_MCLK/LCD_VCPWC B16 PTI5/MD10/ST1_VALID/ LCD_D1 B17 PTI7/IRQ3/IRL3/ST0M_D7I/ IIC1_SDA B18 PTJ4/ST0M_D2I/ET0_ERXD2/ RMII1_RXD1/LCD_CL2 RDY/EX_RDY/PCC_WAIT B19 CS2/EX_CS1 B20 B21 PTM7/D31/EX_AD31/ST0_D7/ ET0_RX-DV/RMII0_TXD0/ PINT7 B22 PTM5/D29/EX_AD29/ST0_D5/ ET0_RX-ER/RMII0_TXD_EN/ PINT5 B23 VSSQ B24 PTM3/D27/EX_AD27/ST0_D3/ ET0_LINKSTA/RMII0_RXD1/ PINT3 ...
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Pin No. Pin Name C5 M_A12 C6 M_A11 C7 M_A9 C8 M_A8 C9 M_A7 C10 M_A6 C11 M_A5 XRTCSTBI C12 C13 VCCQ C14 PTI1/STATUS1/ST1_REQ/ RMII0_MDIO C15 PTK6/ST1_D6/GET0_ERXD6/ SIOF2_SCK/LCD_VEPWC C16 PTI4/MD8/ST1_START/ ET1_PHY-INT/RMII0M0_MDC/ USB_PWREN/USBF_UPLUP C17 PTJ7/INTB/ST0M_D5I/ IRQOUT/RMII1_TXD0/LCD_D0 C18 PTJ3/ST0M_D1I/ET0_ERXD1/ RMII1_CRS_DV/LCD_CL1 CS6/CE1B C19 ...
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Section 1 Overview Pin No. Pin Name C22 VSSQ BS/EX_BS C23 C24 PTM2/D26/EX_AD26/ST0_D2/ ET0_WOL/RMII0_CRS_DV/ PINT2 C25 PTM1/D25/EX_AD25/ST0_D1/ ET0_TX-CLK/RMII0_RX_ER/ PINT1 D1 M_D1 D2 M_D16 D3 VCCQ-DDR D4 VSSQ-DDR D5 VSSQ-DDR D6 VSSQ-DDR D7 VCCQ-DDR D8 VCCQ-DDR D9 VSSQ-DDR D10 VSSQ-DDR D11 ...
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Pin No. Pin Name CS4 D19 D20 VDD D21 VSSQ D22 VCCQ RDWR/EX_RDWR D23 D24 PTM0/D24/EX_AD24/ST0_D0/ ET0_TX-ER/PINT0/ RMII0M0_MDIO D25 PTL7/D23/EX_AD23/ ST0_VALID/ET0_TX-EN/ TEND1/LCD_D15 E1 M_D2 E2 M_D17 E3 M_D18 E4 VCCQ-DDR E5 VCCQ-DDR E6 VSSQ-DDR E7 VCCQ-DDR E8 VDD E9 VSS ...
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Section 1 Overview Pin No. Pin Name E19 VSSQ E20 VSS E21 VCCQ E22 PTK3/ST1_D3/GET0_ETXD7/ SIOF2_SYNC/LCD_D5 E23 PTK2/ST1_D2/GET0_ETXD6/ SIOF1_SCK/LCD_D4 E24 PTL6/D22/EX_AD22/ ST0_START/ET0_ETXD2/ DACK1/LCD_D14 E25 PTL5/D21/EX_AD21/ST0_CLK/ ET0_ETXD1/DREQ1/LCD_D13 F1 M_D3 F2 M_D19 F3 M_D20 F4 VSSQ-DDR F5 VSSQ-DDR F21 VSS F22 PTK1/ST1_D1/GET0_ETXD5/ ...
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Pin No. Pin Name G2 M_D21 G3 M_D22 G4 VCCQ-DDR G5 VCCQ-DDR G21 VDD G22 PTL3/D19/EX_AD19/IRQ7/ IRL7/ET0_MDIO/INTC/ LCD_D11 G23 PTL2/D18/EX_AD18/IRQ6/ IRL6/ET0_ETXD3/TEND0/ LCD_D10 WE3/IOWR G24 WE2/IORD G25 H1 M_D5 H2 M_D23 H3 M_DQS2 H4 VSSQ-DDR H5 VSSQ-DDR H21 VCCQ H22 PTL0/D16/EX_AD16/IRQ4/ ...
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Section 1 Overview Pin No. Pin Name J1 M_D7 J2 M_D6 J3 M_DQM2 J4 VSSQ-DDR J5 VSSQ-DDR J21 VSS J22 D7/EX_AD7 J23 D6/EX_AD6 J24 D13/EX_AD13 J25 D12/EX_AD12 K1 M_DQM0 K2 M_DQS0 K3 M_DQS3 K4 VCCQ-DDR K5 VCCQ-DDR K10 VSS K11 ...
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Pin No. Pin Name L1 M_DQS1 L2 M_DQM1 L3 M_DQM3 L4 VSS-DLL1 L5 VSS-DLL2 L10 VSS L11 VSS L12 VSS L13 VSS L14 VSS L15 VSS L16 VSS L21 VCCQ L22 D3/EX_AD3 L23 D2/EX_AD2 L24 D9/EX_AD9 L25 D8/EX_AD8 M1 M_D8 ...
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Section 1 Overview Pin No. Pin Name M15 VSS M16 VSS M21 VSS M22 D1/EX_AD1 M23 D0/EX_AD0 WE1/WE M24 M25 CLKOUT N1 M_D9 N2 M_D26 N3 M_D27 N4 VCCQ-DDR N5 VCCQ-DDR N10 VSS N11 VSS N12 VSS N13 VSS N14 ...
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Pin No. Pin Name P4 VSSQ-DDR P5 VSSQ-DDR P10 VSS P11 VSS P12 VSS P13 VSS P14 VSS P15 VSS P16 VSS P21 VSSQ P22 A9 P23 A8 P24 A3 P25 A2 R1 M_D11 R2 M_D30 R3 M_D31 R4 VCCQ-DDR ...
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Section 1 Overview Pin No. Pin Name R24 A5 R25 A4 T1 M_D13 T2 M_D12 T3 VSSQ-DDR T4 VCCQ-DDR T5 VCCQ-DDR T10 VSS T11 VSS T12 VSS T13 VSS T14 VSS T15 VSS T16 AVss T21 VSS T22 A17 T23 ...
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Pin No. Pin Name U25 A12 V1 VDD V2 VDD V3 VDD V4 VDD V5 VDD V21 VSS V22 A21 V23 A20 V24 A15 V25 A14 W1 PTG1/GNT2/ET1_ETXD0 W2 PTG2/REQ1/ET1_ETXD1 W3 PTG3/REQ3/ET1_ETXD2 W4 PTF0/GNT0/GNTIN/SIM_D/ ET1_ETXD3/DREQ3 W5 VDD W21 VDD W22 ...
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Section 1 Overview Pin No. Pin Name Y3 PTE0/INTA/PCC_DRV/ GET1_ETXD6/DREQ2 Y4 PTD7/PCIRESET/ PCC_RESET/GET1_ETXD7/ LCDM_VEPWC Y5 VSS Y21 VCCQ CE2A Y22 CE2B Y23 Y24 DA1 Y25 DA0 AA1 PTF1/REQ0/REQOUT/ SIM_CLK/ET1_MDC/DACK3 AA2 PTF2/AD31/SIM_RST/ ET1_MDIO/TEND3 AA3 PTG0/GNT1/ET1_WOL AA4 PTG4/AD30/ET1_LINKSTA AA5 VSSQ AA6 VCCQ ...
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Pin No. Pin Name AA15 VCCQ AA16 VSSQ AA17 VSSQ AA18 VCCQ AA19 VSSQ AA20 VCCQ AA21 VSSQ AA22 VSSQ IOIS16/TMU_TCLK AA23 AA24 AVcc AA25 AVcc AB1 PTE5/AD29/SCIF2_TXD/ GET1_GTX-CLK/SSI0_SCK AB2 PTG7/AD28/ET1_TX-EN AB3 PTG6/AD26/ET1_TX-ER AB4 VSSQ AB5 VCCQ AB6 PTE4/AD22/SCIF2_RXD/ GET1_ERXD4/SSI0_SDATA ...
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Section 1 Overview Pin No. Pin Name AB11 PTB2/AD11/PINT10/LCDM_D7 IO/IO/I/O AB12 PTB6/CBE0/PINT14/ LCDM_D3 AB13 PTC1/AD4/LCDM_D1 AB14 VSSQ AB15 VCCQ AB16 MPMD AB17 PTO6/IRQ0/IRL0/ DACK1M/MD5 AB18 PTO2/AUDATA1/ RMII0M1_MDC AB19 VSSQ AB20 TDO AB21 VSSQ AB22 VSSQ AB23 VCCQ AB24 AN3 AB25 ...
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Pin No. Pin Name AC6 PTE3/AD20/SCIF2_SCK/ GET1_ERXD5/SSI0_WS AC7 PTE2/AD16/PCC_IOIS16/ GET1_ERXD7/TEND2 AC8 PTD2/TRDY/PCC_RDY/ SIOF0_RXD/HAC_SYNC/ LCDM_D11 AC9 PTA0/PAR/SCIF1_SCK AC10 PTA4/AD13/SCIF1_RTS AC11 PTB3/AD9/PINT11/LCDM_D6 AC12 PTB7/AD6/PINT15/LCDM_D2 AC13 PTC2/AD2/LCDM_D0 AC14 PTC5/AD0/MMC_CD/ LCDM_FLM AC15 PTN2/SCIF0_TXD/MD1 MRESET AC16 AC17 PTO7/IRQ1/IRL1/TEND1M/ SSI3_SCK/MD6 AC18 PTO3/AUDATA2/ RMII0M1_MDIO/SSI2_SCK TRST AC19 AC20 ...
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Section 1 Overview Pin No. Pin Name AC24 AN1 AC25 AN0 AD1 PTF3/CBE3/ET1_TX-CLK AD2 VSSQ AD3 VCCQ AD4 PTH2/AD24/TPU_TI2A/ ET1_ERXD0/RMII1M_TXD1 AD5 PTH3/AD21/TPU_TI2B/ ET1_ERXD2/RMII1M_RXD1 AD6 PTH7/AD17/TPU_TO3/ ET1_RX-DV AD7 PTD0/IRDY/PCC_VS1/ SIOF0_SYNC/HAC_SD_IN/ LCDM_D13 AD8 PTA2/LOCK/SCIF1_TXD AD9 PTB1/SERR/PINT9/ LCDM_D9 AD10 PTB5/AD14/PINT13/ LCDM_M_DISP AD11 PTC0/AD10/MMC_DAT/ ...
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Pin No. Pin Name AD17 PTO0/AUDSYNC/ RMII1_MDC/SSI2_WS AD18 PTO4/AUDATA3/EX_INT/ SSI3_WS ASEBRK/BRKACK AD19 AD20 VSS-PLL3 AD21 VSS-PLL2 BREQ AD22 AD23 VCCQ AD24 VSS-PLL1 AD25 AVcc AE1 VSSQ AE2 VCCQ AE3 PTG5/GNT3/ET1_RX-CLK AE4 PTH5/AD23/TPU_TO1/ ET1_ERXD1/RMII1M_TXD0 AE5 PTH4/AD19/TPU_TO0/ ET1_ERXD3/RMII1M_RXD0 AE6 PTD1/CBE2/PCC_VS2/ SIOF0_TXD/HAC_SD_OUT/ LCDM_D15 ...
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Section 1 Overview Pin No. Pin Name AE11 PTC3/AD8/MMC_ODMOD/ LCDM_D4 AE12 PTC6/AD5/LCDM_CL1 AE13 PTA6/AD1/MMC_VDDON AE14 PTN1/SCIF0_RXD/MD3 AE15 PTN4/SCIF0_RTS/MD2 PRESET AE16 AE17 PTO1/AUDATA0/ RMII1_MDIO/SSI2_SDATA AE18 PTO5/AUDCK/DREQ1M/ SSI3_SDATA AE19 TCK AE20 VDD-PLL3 AE21 VDD-PLL2 AE22 EXTAL AE23 XTAL AE24 VDD-PLL1 AE25 VSSQ ...
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Section 2 Programming Model The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below. 2.1 Data Formats The data formats supported in this LSI are shown in figure 2.1. ...
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Section 2 Programming Model 2.2 Register Descriptions 2.2.1 Privileged Mode and Banks (1) Processing Modes This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an ...
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Control Registers Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processing modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register ...
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Section 2 Programming Model Table 2.1 Initial Register Values Type Registers General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1 R15 Control registers SR GBR, SSR, SPC, SGR, DBR Undefined VBR System registers MACH, MACL Floating-point FR0 ...
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R0 _ BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 R10 ...
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Section 2 Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of ...
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Note on Programming: As the user are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt are assigned to R0_BANK1 to R7_BANK1 not necessary for the interrupt handler to save ...
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Section 2 Programming Model 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF4 XF1 XF5 XF2 XF6 XF3 XF7 FPSCR.FR=0 FV0 DR0 FR0 FR1 DR2 FR2 FR3 FV4 DR4 FR4 FR5 DR6 ...
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Control Registers (1) Status Register (SR) BIt Initial value R/W: R R/W R/W R/W BIt Initial value R/W: R Initial Bit Bit ...
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Section 2 Programming Model Initial Bit Bit Name Value — All — All IMASK All — All ...
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Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined) The contents of SR are saved to SSR in the event of an exception or interrupt. (3) Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value ...
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Section 2 Programming Model (4) Floating-Point Status/Control Register (FPSCR) BIt Initial value R/ BIt Cause Initial value R/W: R/W R/W R/W R/W Initial Bit Bit ...
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Initial Bit Bit Name Value Cause All Enable (EN) All Flag All R/W Description R/W FPU Exception Cause Field FPU Exception Enable Field R/W ...
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Section 2 Programming Model <Big endian> 63 Floating-point register 63 FR (2i) 63 Memory area 8n <Little endian> 63 Floating-point register 63 FR (2i) 63 Memory area 4n+3 Notes the case and PR = ...
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Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. • H'1C00 ...
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Section 2 Programming Model 2.4 Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded into ...
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Address A Byte 0 15 Address Word 0 31 Address For the 64-bit data format, see figure 2.5. 2.6 Processing States This LSI has major three processing states: the ...
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Section 2 Programming Model From any state when reset/manual reset input Reset/manual reset clearance Instruction execution state Figure 2.8 Processing State Transitions Rev. 2.00 May 22, 2009 Page 54 of 1982 REJ09B0256-0200 Reset state Reset/manual reset input Sleep instruction execution ...
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Usage Note 2.7.1 Notes on Self-Modified Codes* This LSI prefetches instructions more drastically than conventional SH-4 to accelerate the processing speed. Therefore if the instruction in the memory is modified and it is executed immediately, then the pre-modified code ...
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Section 2 Programming Model Rev. 2.00 May 22, 2009 Page 56 of 1982 REJ09B0256-0200 ...
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Section 3 Instruction Set This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved ...
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Section 3 Instruction Set T Bit: The T bit used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is ...
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Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If ...
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Section 3 Instruction Set Addressing Instruction Mode Format Register @–Rn indirect with pre- decrement Register @(disp:4, Rn) Effective address is register Rn contents with indirect with displacement Indexed @(R0, Rn) register indirect Rev. 2.00 May 22, 2009 Page 60 of ...
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Addressing Instruction Mode Format GBR indirect @(disp:8, with GBR) displacement Indexed GBR @(R0, GBR) indirect PC-relative @(disp:8, PC) Effective address with 8-bit with displacement Effective Address Calculation Method Effective address is register GBR contents with 8-bit ...
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Section 3 Instruction Set Addressing Instruction Mode Format PC-relative disp:8 PC-relative disp:12 Rn Rev. 2.00 May 22, 2009 Page 62 of 1982 REJ09B0256-0200 Effective Address Calculation Method Effective address with 8-bit displacement disp added after being ...
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Addressing Instruction Mode Format Immediate #imm:8 #imm:8 #imm:8 Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the operand ...
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Section 3 Instruction Set 3.3 Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Instruction OP.Sz SRC, DEST mnemonic Operation notation ...
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Item Format Privileged mode T bit Value of T bit after instruction execution New Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand. Description "Privileged" means the instruction can only be ...
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Section 3 Instruction Set Table 3.4 Fixed-Point Transfer Instructions Instruction Operation imm → sign extension → Rn #imm,Rn MOV (disp × → sign MOV.W @(disp*,PC),Rn extension → Rn (disp × & H'FFFF ...
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Instruction Operation (R0 + Rm) → MOV.W @(R0,Rm),Rn sign extension → Rn (R0 + Rm) → Rn MOV.L @(R0,Rm),Rn R0 → (disp + GBR) MOV.B R0,@(disp*,GBR) R0 → (disp × GBR) MOV.W R0,@(disp*,GBR) R0 → (disp × 4 ...
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Section 3 Instruction Set Table 3.5 Arithmetic Operation Instructions Instruction Operation → Rn ADD Rm,Rn #imm, imm → Rn ADD → Rn, ADDC Rm,Rn carry → ...
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Instruction Operation DMULU.L Rm,Rn Unsigned, Rn × Rm → MAC, 32 × 32 → 64 bits Rn – 1 → Rn when → T When Rn ≠ → T EXTS.B Rm,Rn Rm ...
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Section 3 Instruction Set Table 3.6 Logic Operation Instructions Instruction Operation Rn & Rm → Rn AND Rm,Rn R0 & imm → R0 AND #imm,R0 AND.B (R0 + GBR) & imm #imm,@(R0,GBR) → (R0 + GBR) ~Rm → Rn NOT ...
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Table 3.7 Shift Instructions Instruction Operation T ← Rn ← MSB ROTL Rn LSB → Rn → T ROTR Rn T ← Rn ← T ROTCL Rn T → Rn → T ROTCR Rn When Rm ≥ << ...
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Section 3 Instruction Set Table 3.8 Branch Instructions Instruction Operation When disp × label 4 → PC When nop BF/S label Delayed branch; when disp × ...
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Instruction Operation Rm → SGR LDC Rm,SGR Rm → SSR LDC Rm,SSR Rm → SPC LDC Rm,SPC Rm → DBR LDC Rm,DBR Rm → Rn_BANK ( LDC Rm,Rn_BANK (Rm) → SR → Rm ...
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Section 3 Instruction Set Instruction Operation 1 → T SETT SLEEP Sleep or standby SR → Rn STC SR,Rn GBR → Rn STC GBR,Rn VBR → Rn STC VBR,Rn SSR → Rn STC SSR,Rn SPC → Rn STC SPC,Rn SGR ...
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Table 3.10 Floating-Point Single-Precision Instructions Instruction Operation H'0000 0000 → FRn FLDI0 FRn H'3F80 0000 → FRn FLDI1 FRn FRm → FRn FMOV FRm,FRn (Rm) → FRn FMOV.S @Rm,FRn @(R0,Rm),FRn (R0 + Rm) → FRn FMOV.S (Rm) → FRn, Rm ...
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Section 3 Instruction Set Table 3.11 Floating-Point Double-Precision Instructions Instruction Operation FABS DRn DRn & H'7FFF FFFF FFFF FFFF → DRn DRn + DRm → DRn FADD DRm,DRn When DRn = DRm, 1 → T FCMP/EQ DRm,DRn Otherwise, 0 → ...
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Table 3.13 Floating-Point Graphics Acceleration Instructions Instruction Operation DRm → XDn FMOV DRm,XDn XDm → DRn FMOV XDm,DRn XDm → XDn FMOV XDm,XDn (Rm) → XDn FMOV @Rm,XDn (Rm) → XDn → Rm FMOV @Rm+,XDn @(R0,Rm),XDn (R0 ...
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Section 3 Instruction Set Rev. 2.00 May 22, 2009 Page 78 of 1982 REJ09B0256-0200 ...
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This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. 4.1 Pipelines Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of seven stages: instruction fetch (I1/I2), decode ...
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Section 4 Pipelining Figure 4.2 shows the instruction execution patterns. Representations in figure 4.2 and their descriptions are listed in table 4.1. Table 4.1 Representations of Instruction Execution Patterns Representation ...
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BF, BF/S, BT, BT/S, BRA, BSR E1/S1 (I1) 1 issue cycle + 3 branch cycles (1-2) JSR, JMP, BRAF, BSRF E1/S1 1 issue cycle ...
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Section 4 Pipelining (2-1) 1-step operation (EX type): 1 issue cycle EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT Note: Except for ...
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Load/store: 1 issue cycle MOV.[BWL], MOV.[BWL] @(d,GBR (3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles (3-3) TAS.B: 4 issue cycles (3-4) PREF, OCBI, OCBP, OCBWB, ...
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Section 4 Pipelining (4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle I1 I2 (4-2) LDC to DBR/SGR: 4 issue cycles I1 I2 (4-3) LDC to GBR: 1 issue cycle I1 I2 (4-4) LDC to SR: 4 issue cycles + 3 branch ...
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STC from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-10) STC from SR: 1 issue cycle E1s1 (4-11) STC.L from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-12) STC.L from SR: 1 issue cycle ...
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Section 4 Pipelining (5-1) LDS to MACH/L: 1 issue cycle I1 I2 (5-2) LDS.L to MACH/L: 1 issue cycle I1 I2 (5-3) STS from MACH/L: 1 issue cycle I1 I2 (5-4) STS.L from MACH/L: 1 issue cycle I1 I2 (5-5) ...
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LDS to FPUL: 1 issue cycle FS1 (6-2) STS from FPUL: 1 issue cycle FS1 s1 (6-3) LDS.L to FPUL: 1 issue cycle FS1 (6-4) STS.L from FPUL: ...
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Section 4 Pipelining (6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle (6-13) FLDI0, FLDI1: 1 issue cycle (6-14) Single-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, ...
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FIPR: 1 issue cycle FE1 (6-20) FTRV: 1 issue cycle FE1 (6-21) FSRRA: 1 issue cycle FE1 (6-22) FSCA: 1 issue cycle FE1 Figure 4.2 Instruction Execution ...
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Section 4 Pipelining 4.2 Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 4.2. Table 4.3 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in ...
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Instruction Group LS FABS FNEG FLDI0 FLDI1 FLDS FMOV @adr,FR FMOV FR,@adr FMOV FR,FR FMOV.S @adr,FR FE FADD FSUB FCMP (S/D) FCNVDS FCNVSD CO AND.B #imm,@(R0,GBR) ICBI LDC Rm,DBR LDC Rm, SGR LDC Rm,SR LDC.L @Rm+,DBR LDC.L @Rm+,SGR [Legend] R: ...
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Section 4 Pipelining The parallel execution of two instructions can be carried out under following conditions. 1. Both addr (preceding instruction) and addr+2 (following instruction) are specified within the minimum page size (1 Kbyte). 2. The execution of these two ...
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Table 4.3 Combination of Preceding and Following Instructions EX Following EX No Instruction MT Yes (addr+2) BR Yes LS Yes FE Yes CO No Note: The following table shows the parallel-executability of pairs of instructions in this LSI ...
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Section 4 Pipelining 4.3 Issue Rates and Execution Cycles Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4 corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not ...
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Table 4.4 Issue Rates and Execution Cycles Functional Category No. Instruction Data transfer 1 EXTS.B instructions 2 EXTS.W 3 EXTU.B 4 EXTU.W 5 MOV 6 MOV 7 MOVA 8 MOV.W 9 MOV.L 10 MOV.B 11 MOV.W 12 MOV.L 13 MOV.B ...
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Section 4 Pipelining Functional Category No. Instruction Data transfer 30 MOV.L instructions 31 MOV.B 32 MOV.W 33 MOV.L 34 MOV.B 35 MOV.W 36 MOV.L 37 MOV.B 38 MOV.W 39 MOV.L 40 MOVCA.L 41 MOVCO.L 42 MOVLI.L 43 MOVUA.L 44 MOVUA.L ...
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Functional Category No. Instruction Fixed-point 60 CMP/GT arithmetic 61 CMP/HI instructions 62 CMP/HS 63 CMP/PL 64 CMP/PZ 65 CMP/STR 66 DIV0S 67 DIV0U 68 DIV1 69 DMULS.L 70 DMULU MAC.L 73 MAC.W 74 MUL.L 75 MULS.W 76 ...
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Section 4 Pipelining Functional Category No. Instruction Logical 91 TST instructions 92 TST.B 93 XOR 94 XOR 95 XOR.B Shift 96 ROTL instructions 97 ROTR 98 ROTCL 99 ROTCR 100 SHAD 101 SHAL 102 SHAR 103 SHLD 104 SHLL 105 ...
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Functional Category No. Instruction Branch 121 JSR instructions 122 RTS System 123 NOP control 124 CLRMAC instructions 125 CLRS 126 CLRT 127 ICBI 128 SETS 129 SETT 130 PREFI 131 SYNCO 132 TRAPA 133 RTE 134 SLEEP 135 LDTLB 136 ...
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Section 4 Pipelining Functional Category No. Instruction System 151 LDC.L control 152 LDS instructions 153 LDS 154 LDS 155 LDS.L 156 LDS.L 157 LDS.L 158 STC 159 STC 160 STC 161 STC 162 STC 163 STC 164 STC 165 STC ...
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Functional Category No. Instruction Single- 180 FLDI0 precision 181 FLDI1 floating-point 182 FMOV instructions 183 FMOV.S 184 FMOV.S 185 FMOV.S 186 FMOV.S 187 FMOV.S 188 FMOV.S 189 FLDS 190 FSTS 191 FABS 192 FADD 193 FCMP/EQ 194 FCMP/GT 195 FDIV ...
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Section 4 Pipelining Functional Category No. Instruction Double- 210 FABS precision 211 FADD floating-point 212 FCMP/EQ instructions 213 FCMP/GT 214 FCNVDS 215 FCNVSD 216 FDIV 217 FLOAT 218 FMUL 219 FNEG 220 FSQRT 221 FSUB 222 FTRC FPU system 223 ...
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Functional Category No. Instruction Graphics 241 FRCHG acceleration 242 FSCHG instructions 243 FPCHG 244 FSRRA 245 FSCA 246 FTRV Instruction Group FRn FE FPUL,DRn FE XMTRX,FVn FE Section 4 Pipelining Execution Execution Issue Rate Cycles Pattern 1 ...
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Section 4 Pipelining Rev. 2.00 May 22, 2009 Page 104 of 1982 REJ09B0256-0200 ...
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Section 5 Exception Handling 5.1 Summary of Exception Handling Exception handling processing is handled by a special routine which is executed by a reset, general exception handling, or interrupt. For example, if the executing instruction ends abnormally, appropriate action must ...
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Section 5 Exception Handling 5.2.1 TRAPA Exception Register (TRA) The TRAPA exception register (TRA) consists of 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be ...
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Exception Event Register (EXPEVT) The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when ...
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Section 5 Exception Handling 5.2.3 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. Bit: ...
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Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), ...
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Section 5 Exception Handling 5.4 Exception Types and Priorities Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.3 Exceptions Exception Execution Category Mode Exception Reset Abort type Power-on reset Manual reset ...
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Exception Execution Category Mode Exception General Completion Unconditional trap (TRAPA) exception type User break after instruction execution* Interrupt Completion Nonmaskable interrupt type General interrupt request Notes: 1. When UBDE in CBCR = DBR. In other cases, PC ...
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Section 5 Exception Handling 5.5 Exception Flow 5.5.1 Exception Flow Figure 5.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, ...
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Yes Reset requested? No Execute next instruction General Yes exception requested? No Yes Interrupt requested? SSR ← SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 SR.IMASK ← received interuupt level (*) PC ← ...
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Section 5 Exception Handling 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—general illegal instruction exception, slot ...
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Exception Requests and BL Bit When the BL bit exceptions and interrupts are accepted. When the BL bit and an exception other than a user break is generated, the CPU's internal ...
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Section 5 Exception Handling 5.6 Description of Exceptions The various exception handling operations explained here are exception sources, transition address on the occurrence of exception, and processor operation when a transition is made. 5.6.1 Resets (1) Power-On Reset • Condition: ...
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Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A0000000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) ...
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Section 5 Exception Handling 5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is ...
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Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual ...
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Section 5 Exception Handling (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit • Transition address: VBR + H'00000100 • Transition operations: The virtual address (32 bits) at which ...
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Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. PR Privileged Mode 00 Only read access possible 01 Read/write access possible 10 Only read access possible 11 ...
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Section 5 Exception Handling (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. PR Privileged Mode 0 Access possible 1 Access possible • Transition address: VBR + ...
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Data Address Error • Sources: Word data access from other than a word boundary (2n +1) Longword data access from other than a longword data boundary (4n + +3) Quadword data ...
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Section 5 Exception Handling (7) Instruction Address Error • Sources: Instruction fetch from other than a word boundary (2n +1) Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 to H'E5FFFFFF can be accessed in ...
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Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'00000100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value ...
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Section 5 Exception Handling (9) General Illegal Instruction Exception • Sources: Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding ...
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Slot Illegal Instruction Exception • Sources: Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding of an instruction that modifies ...
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Section 5 Exception Handling (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR. • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for ...
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Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'00000100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in ...
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Section 5 Exception Handling (13) Pre-Execution User Break/Post-Execution User Break • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'00000100, or DBR • Transition operations: In the case of a post-execution ...