R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 664

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
Table 14.6 Selecting External Request Detection with DL, DS Bits
When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing
acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept
enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
• Overrun 0: Transfer is aborted after the same number of transfer has been performed as
• Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 14.7 Selecting External Request Detection with DO Bit
(3)
In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module.
Transfer request signals comprise the transmit data empty transfer request and receive data full
transfer request from the SCIF0 to SCIF2, HAC USBF, SSI0 to SSI3, MMCIF, SIM, SIOF0 to
SIOF2, STIF0, and STIF1 set by DMARS0/1/2, and transfer requests from the CMT.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
Rev. 2.00 May 22, 2009 Page 594 of 1982
REJ09B0256-0200
DL
0
1
CHCR
DO
0
1
requests.
plus 1) times.
On-Chip Peripheral Module Request Mode
CHCRn (n=0 to 3)
DS
0
1
0
1
External Request
Overrun 0 (initial value)
Overrun 1
Detection of External Request
Low level detection (initial value; DREQ)
Falling edge detection
High level detection
Rising edge detection