R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1304

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 29 Serial I/O with FIFO (SIOF)
(4)
Figure 29.12 shows an example of settings and operation for slave mode reception.
Rev. 2.00 May 22, 2009 Page 1234 of 1982
REJ09B0256-0200
No.
1
2
3
4
5
6
Reception in Slave Mode
Store SIOFRXD receive data in SIRDR
synchronously with SIOF_SYNC
Clear the RXE bit in SICTR to 0
Set SIMDR, SISCR, SIRDAR,
Set the RXE bit in SICTR to 1
SICDAR, and SIFCTR
Figure 29.12 Example of Receive Operation in Slave Mode
RDREQ = 1?
Read SIRDR
Flow Chart
Transfer
ended?
Start
End
Yes
Yes
No
No
Set operating mode, serial clock,
slot positions for receive data,
slot position for control data, and
FIFO request threshold value
Set to enable reception
Read receive data
Set to disable reception
SIOF Settings
Enable reception when the
frame synchronous signal is
input
Issue receive transfer request
according to the receive
FIFO threshold value
Reception
End reception
SIOF Operation

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