R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 214

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Memory Management Unit (MMU)
The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address
array. For details, see section 7.6.3, OC Address Array.
The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data
array. For details, see section 7.6.4, OC Data Array.
The area from H'F600 0000 to H'F60F FFFF is used for direct access to the unified TLB address
array. For details, see section 6.6.3, UTLB Address Array.
The area from H'F700 0000 to H'F70F FFFF is used for direct access to unified TLB data array.
For details, see section 6.6.4, UTLB Data Array.
The area from H'F610 0000 to H'F61F FFFF is used for direct access to the PMB address array.
For details, see section 6.7.5, Memory-Mapped PMB Configuration.
The area from H'F710 0000 to H'F71F FFFF is used for direct access to the PMB data array. For
details, see section 6.7.5, Memory-Mapped PMB Configuration.
The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register
area. For details, see register descriptions in each section.
Physical Address Space: This LSI supports a 29-bit physical address space. The physical address
space is divided into eight areas as shown in figure 6.5. Area 7 is a reserved area.
Only when area 7 in the physical address space is accessed using the TLB, addresses H'1C00 0000
to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the control
register area in the P4 area in the virtual address space.
Rev. 2.00 May 22, 2009 Page 144 of 1982
REJ09B0256-0200
Figure 6.5 Physical Address Space
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'1FFF FFFF
Area 7 (reserved area)
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6

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