R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 565

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(6)
PCIIR records the source of an interrupt.
When multiple interrupts occur, only the first source is registered.
When an interrupt is disabled, the source is registered in corresponding bit (set to 1) in this
register, however, no interrupt occurs.
Initial value:
Initial value:
Bit
31 to 15 
14
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Interrupt Register (PCIIR)
Bit:
Bit:
Bit Name
TTADI
31
15
—
—
R
R
R
R
0
0
R/WC
TTA
30
14
—
DI
R
R
R
0
0
29
13
Initial
Value
All 0
0
—
—
R
R
R
R
0
0
28
12
—
—
R
R
R
R
0
0
R/W
SH: R
PCI: R
SH: R/WC
PCI: R
27
11
—
—
R
R
R
R
0
0
26
10
—
—
R
R
R
R
0
0
R/WC
TMT
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Target Target-Abort Interrupt
Indicates that the PCIC has terminated a transaction
with a target-abort when the PCIC functions as a
target.
A target-abort is detected as an illegal byte enable
when the lower two bits (bits 1 and 0) of the address
and the byte enable do not match during an I/O
transfer (target).
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
25
—
OI
R
R
R
0
9
0
R/WC
MDEI
24
—
R
R
R
0
8
0
R/WC
APE
23
—
DI
R
R
R
0
7
0
R/WC
Rev. 2.00 May 22, 2009 Page 495 of 1982
SE
22
—
DI
R
R
R
0
6
0
R/WC
DPEI
TW
21
—
R
R
R
0
5
0
Section 13 PCI Controller (PCIC)
R/WC
DPEI
TR
20
—
R
R
R
0
4
0
R/WC
TAD
19
IM
—
R
R
R
0
3
0
R/WC
REJ09B0256-0200
MAD
18
IM
—
R
R
R
0
2
0
R/WC
MW
PDI
17
—
R
R
R
0
1
0
R/WC
MRD
PEI
16
—
R
R
R
0
0
0