R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 920

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 2.00 May 22, 2009 Page 850 of 1982
REJ09B0256-0200
Bit
5 to 0
Bit Name
BSYSL1[5:0] All 1
Initial
Value
R/W
R/W
Description
These bits set the threshold of the port 1-to-0 relay
FIFO size in 256-byte units when the TSU alerts the E-
MAC-1 that writing in the relay FIFO will be disabled
during relay operations.
H'00: 0 byte
H'01: 256 bytes
H'02: 512 bytes
H'16: 5632 bytes
H'17: 5888 bytes
Settings are disabled for H'18 to H'3F. (Alert is not
always carried out.)
When the data volume written in the relay FIFO
exceeds the threshold set in these bits, the TSU alerts
the E-MAC-1 that writing in the relay FIFO will be
disabled. Thereafter, alerting will be stopped when the
data volume written in the relay FIFO becomes 16
bytes smaller than this threshold.
When H'00 is set, the TSU always alerts the E-MAC-1
that writing to the relay FIFO will be disabled. When the
value set is equal to or higher than the port 1-to-0 relay
FIFO size set by bits FCM[2:0] in TSU_FCM, the TSU
does not alert the E-MAC-1 that writing in the relay
FIFO will be disabled.
This register must not be written to once after relay
operations have been enabled (after the FWEN0 bit in
TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set
to 1).
When the enable bit of relay operations (FWEN0 bit in
TSU_FWEN0 or FWEN1 bit in TSU_FWEN1) is cleared
to 0, the TSU stops alerting the E-MAC-1 that writing in
the relay FIFO will be disabled.
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