HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 475

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16.1
There are three ports, A, B, and C. Ports A and B are 16-bit I/O ports, while port C is an 8-bit
input port. The pins of the ports are all multiplexed for use as general-purpose I/Os (or inputs in
the case of port C) or for other functions. (Use the pin function controller (PFC) to select the
function of multiplexed pins.) Ports A, B, and C each have one data register for storing pin data.
16.2
Port A is a 16-pin input/output port, as shown in figure 16.1. The PA3/CS7/WAIT pin of port A
has a pull-up MOS so that when it is functioning as a WAIT pin, the wait state control register of
the bus state controller can be used to select whether to pull up the WAIT pin or not. It is not
pulled up when the pin is functioning as either PA3 or CS7.
16.2.1
Table 16.1 summarizes the port A register.
Overview
Register Configuration
Port A
Port A
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Section 16 I/O Ports (I/O)
(Input/output)/AH (Output)/IRQOUT (Output)/ADTRG (Input)
(Input/output)/BREQ (Input)
(Input/output)/BACK (Output)
(Input/output)/RD (Output)
(Input/output)/WRH (Output) (LBS (Output))
(Input/output)/WRL (Output) (WR (Output))
(Input/output)/CS7 (Output)/WAIT (Input)
(Input/output)/CS6 (Output)/TIOCB0 (Input/output)
(Input/output)/CS5 (Output)/RAS (Output)
(Input/output)/CS4 (Output)/TIOCA0 (Input/output)
(Input/output)/IRQ3 (Input)/DREQ1 (Input)
(Input/output)/IRQ2 (Input)/DACK1 (Output)
(Input/output)/IRQ1 (Input)/DREQ0 (Input)/TCLKB (Input)
(Input/output)/IRQ0 (Input)/DACK0 (Output)/TCLKA (Input)
(Input/output)/DPH (Input/output)/TIOCB1 (Input/output)
(Input/output)/DPL (Input/output)/TIOCA1 (Input/output)
Figure 16.1 Port A Configuration
Rev. 7.00 Jan 31, 2006 page 447 of 658
Section 16 I/O Ports (I/O)
REJ09B0272-0700