HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 151
HD6417032F20V
Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet
1.HD6417034AFI20.pdf
(689 pages)
Specifications of HD6417032F20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
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To prevent RTCSR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'69 is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
8.2.9
The refresh time constant register (RTCOR) is a 16-bit read/write register that sets the compare
match cycle used with RTCNT. The values in RTCOR and RTCNT are constantly compared.
When they match, the compare match flag (CMF) is set in RTCNT and RTCSR is cleared to
H'0000. If the RFSHE bit in RCR is set to 1 when this happens, a CAS-before-RAS (CBR) refresh
is performed. When the CMIE bit in RTCSR is also set to 1, a compare match interrupt (CMI) is
generated.
Bits 15–8 are reserved and cannot be used to set the cycle. These bits are always read as 0.
RTCOR is initialized to H'00FF by a power-on reset, but is not initialized by a manual reset or in
standby mode.
To prevent RTCOR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'96 is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Refresh Time Constant Register (RTCOR)
R/W
15
15
—
—
—
—
0
7
0
0
R/W
14
14
—
—
—
—
0
6
0
0
R/W
13
13
—
—
—
—
0
5
0
0
R/W
12
12
—
—
—
—
0
4
0
0
Rev. 7.00 Jan 31, 2006 page 123 of 658
Section 8 Bus State Controller (BSC)
R/W
11
11
—
—
—
—
0
3
0
0
R/W
10
10
—
—
—
—
0
2
0
0
REJ09B0272-0700
R/W
—
—
—
—
9
0
1
0
9
0
R/W
—
—
—
—
8
0
0
0
8
0
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