HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 116

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 User Break Controller (UBC)
6.2.3
The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four
break conditions:
A reset initializes BBR to H'0000. It is not initialized in standby mode.
Bits 15–8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMA Cycle Select (CD1 and CD0): CD1 and CD0 select whether to
break on CPU and/or DMA bus cycles.
Bit 7: CD1
0
1
Rev. 7.00 Jan 31, 2006 page 88 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
CPU cycle or DMA cycle
Instruction fetch or data access
Read or write
Operand size (byte, word, longword)
Break Bus Cycle Register (BBR)
Bit 6: CD0
0
1
0
1
CD1
R/W
15
—
—
0
7
0
Description
No break interrupt occurs
Break only on CPU cycles
Break only on DMA cycles
Break on both CPU and DMA cycles
CD0
R/W
14
—
—
0
6
0
R/W
ID1
13
—
—
0
5
0
R/W
ID0
12
—
—
0
4
0
RW1
R/W
11
—
—
0
3
0
RW0
R/W
10
—
—
0
2
0
R/W
SZ1
—
—
9
0
1
0
(Initial value)
R/W
SZ0
—
—
8
0
0
0