HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 188

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
Self-Refresh Mode: Some DRAMs have a self-refresh mode (battery back-up mode). This is a
type of a standby mode in which the refresh timing and refresh addresses are generated inside the
DRAM chip. When the RFSHE and RMODE bits in RCR are both set to 1, the DRAM will enter
self-refresh mode when the CAS and RAS signals are output as shown in figure 8.31. See sections
20.1.3 (3) and 20.2.3 (3), Bus Timing, for details. DRAM self-refresh mode is cleared when the
RMODE bit in RCR is cleared to 0 (figure 8.31). The RFSHE bit should be left at 1 when this is
done. Some DRAM vendors recommend that after exiting self-refresh mode, all row addresses
should be refreshed again. This can be done using the BSC’s CBR refresh function to set all row
addresses for refresh in software.
To access a DRAM area while in self-refresh mode, first clear the RMODE bit to 0 and exit self-
refresh mode.
The chip can be kept in the self-refresh state and shifted to standby mode by setting it to self-
refresh mode, setting the standby bit (SBY) in the standby control register (SBYCR) to 1, and then
executing a SLEEP instruction.
Refresh Requests and Bus Cycle Requests: When a CAS-before-RAS refresh or self-refresh is
requested during bus cycle execution, parallel execution is sometimes possible. Table 8.11
summarizes the operation when refresh and bus cycles are in contention.
Rev. 7.00 Jan 31, 2006 page 160 of 658
REJ09B0272-0700
RAS
CAS
CK
T
Rp
Figure 8.31 Output Timing for Self-Refresh Signal
T
Rr
T
Rc
T
Rcc