HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 190

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Section 8 Bus State Controller (BSC)
8.6
The BSC is equipped with a function that multiplexes address and data input/output on pins
AD15–AD0 in area 6. This allows the SH microprocessor to be directly connected to peripheral
chips that require address/data multiplexing.
8.6.1
When the multiplexed I/O enable bit (IOE) in BCR is set to 1, the area 6 space with address bit
A27 as 0 (H'6000000–H'6FFFFFF) becomes an address/data multiplexed I/O space that, when
accessed, multiplexes addresses and data. When the A14 address bit is 0, the bus width is 8 bits
and address output and data input/output are performed on the AD7–AD0 pins. When the A14
address bit is 1, the bus width is 16 bits and address output and data input/output are performed on
the AD15–AD0 pins. In the address/data multiplexed I/O space, access is controlled with the AH,
RD, and WR signals. Accesses in the address/data multiplexed I/O space are performed in 4 states,
regardless of the WCR settings. Figure 8.32 shows the timing when the address/data multiplexed
I/O space is accessed.
Rev. 7.00 Jan 31, 2006 page 162 of 658
REJ09B0272-0700
Read
Write
Address/Data Multiplexed I/O Space Access
Basic Timing
Figure 8.32 Access Timing For Address/Data Multiplexed I/O Space
WRH, WRL
AD15–AD0
AD15–AD0
A21–A0
RD
CK
CS
AH
T1
Address
Address
T2
T3
Data (input)
Data (output)
T4

Related parts for HD6417032F20V