HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 409

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
Transmitting and Receiving Data (SCI initialization (Asynchronous Mode)): Before
transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register
(SCR), then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCI operation becomes unreliable if the clock is stopped.
Figure 13.4 shows a sample flowchart for initializing the SCI. The procedure for initializing the
SCI is as follows:
1. Select the communication format in the serial mode register (SMR).
2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external
3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE,
4.
Figure 13.3 Phase Relationship Between Output Clock and Serial Data (Asynchronous
clock is used.
and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts
immediately after the setting is made in SCR.
Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the
serial control register (SCR) to 1. Also set RIE, TIE, TEIE, and MPIE as necessary. Setting
TE or RE enables the SCI to use the TxD or RxD pin. The initial states are the mark transmit
state, and the idle receive state (waiting for a start bit).
0
D0
D1
D2
D3
1 frame
D4
D5
Mode)
Section 13 Serial Communication Interface (SCI)
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Rev. 7.00 Jan 31, 2006 page 381 of 658
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