HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 420

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
3.
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the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI
requests a transmit-data-empty interrupt (TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin (figure 13.11):
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits are output, LSB first.
c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output.
d. Stop bit: one or two 1-bits (stop bits) are output.
e. Mark state: output of 1-bits continues until the start bit of the next transmit data.
TDRE
TEND
Serial
The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If
TDRE is 1, the SCI sets the TEND bit in SSR to 1, outputs the stop bit, then continues output
of 1-bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a
transmit-end interrupt (TEI) is requested at this time.
Figure 13.11 Example of SCI Multiprocessor Transmit Operation (8-Bit Data with
data
request
1
TXI
Start
bit
clears TDRE to 0
0
data in TDR and
handler writes
TXI interrupt
D
0
D
1 frame
1
Multiprocessor Bit and One Stop Bit)
Data
D
7
processor
Multi-
bit
0/1
request
TXI
Stop
1
bit
Start
bit
0
D
0
D
1
Data
D
7
processor
Multi-
bit
0/1
request
TEI
Stop
bit
1
Idle (mark)
state
1